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公开(公告)号：US07054184B2
公开(公告)日：2006-05-30
申请号：US10844296
申请日：2004-05-12
CPC分类号： G11C11/417 , G11C11/41 , G11C2029/3202
摘要： A late select circuit topology has pseudo-static circuits that provide fast dynamic circuit operation without the use of dynamic clock timing signals. An output from a selected set is enabled by the conjunction of bit line pulse and set select signal.
摘要翻译： 迟选择电路拓扑具有伪静态电路，其在不使用动态时钟定时信号的情况下提供快速动态电路操作。 来自所选集合的输出由位线脉冲和置位选择信号的结合使能。
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公开(公告)号：US06788112B1
公开(公告)日：2004-09-07
申请号：US10436229
申请日：2003-05-12
IPC分类号： G01R1900
CPC分类号： G11C11/419 , G11C7/062 , G11C7/065
摘要： A sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line respectively, to reduce the capacitive load on the first sense line and second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage, the second sensing stage is activated by a sense enable signal following a selected delay, and an output driver responsive to the second sensing stage.
摘要翻译： 一种用于存储器件的读出放大器，包括：第一感测级，包括分别可操作地连接到第一感测线和第二感测线的第一感测装置和第二感测装置，以减小第一感测线和第二感测线上的电容性负载 线。 感测装置的源极端子连接到可切换的电流接收器，其漏极端子连接到第二感测级的输入端。 感测放大器还包括第二感测级，其包括响应于第一感测级的交叉耦合的反相器，第二感测级由响应于所选择的延迟的感测使能信号和响应于第二感测级的输出驱动器激活。
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公开(公告)号：US07592851B2
公开(公告)日：2009-09-22
申请号：US12021454
申请日：2008-01-29
申请人： Yuen H. Chan , Ann H. Chen , Antonio R. Pelella , Shie-ei Wang
发明人： Yuen H. Chan , Ann H. Chen , Antonio R. Pelella , Shie-ei Wang
IPC分类号： H03K17/00
CPC分类号： H03K17/693 , H03K17/005
摘要： A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge.
摘要翻译： 高性能，集合关联的高速缓存存储器标签多路复用器通过分离评估和恢复路径以及在还原路径中比在评估路径中使用更宽的时钟，提供宽的输出脉冲宽度而不影响保持时间。 时钟控制输入信号的评估。 其前沿（即上升沿）打开NR以允许评估，其后沿（下降沿）关闭NR以停止评估。 此时，当NR关闭时，输入可以开始改变以设置下一个周期。 因此，输入的保持时间由时钟后沿决定。
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公开(公告)号：US07272030B2
公开(公告)日：2007-09-18
申请号：US11554072
申请日：2006-10-30
申请人： Yuen H. Chan , Ryan T. Freese , Antonio R. Pelella , Uma Srinivasan , Arthur D. Tuminaro , Jatinder K. Wadhwa
发明人： Yuen H. Chan , Ryan T. Freese , Antonio R. Pelella , Uma Srinivasan , Arthur D. Tuminaro , Jatinder K. Wadhwa
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C7/12 , G11C11/417
摘要： A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck1), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.
摘要翻译： 多米诺SRAM阵列恢复脉冲发生系统通过与恢复脉冲相同的本地时钟启动工作解码线，从而消除了字线选择的任何种族问题。 该系统允许全局位选择（或列选择）通过释放复位信号（具有最早到达的阵列时钟ck 1）来快速激活，同时保证使用位解码系统几乎完美的跟踪。 这允许最广泛的写入窗口; 全局列中最早发布预充电选择，仅在位解码系统被禁用后进行复位。
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公开(公告)号：US07336546B2
公开(公告)日：2008-02-26
申请号：US11054309
申请日：2005-02-09
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.
摘要翻译： 多米诺SRAM全局位选择电路提供了双局域读和写位线对之间的接口到“本地位选择”电路。
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6.发明授权公开(公告)号：US07463537B2
公开(公告)日：2008-12-09
申请号：US11933625
申请日：2007-11-01
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.
摘要翻译： 多米诺SRAM全局位选择电路提供了双局域读和写位线对之间的接口到“本地位选择”电路。
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公开(公告)号：US07113433B2
公开(公告)日：2006-09-26
申请号：US11054402
申请日：2005-02-09
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C7/12 , G11C7/18 , G11C2207/002
摘要： A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors. Separate read and write global “bit line” pairs allow the read and write performance to be optimized independently.
摘要翻译： 多米诺SRAM提供有有源上拉PFET器件，它们淹没“读写速度慢但读取速度非常快”，并允许单元从定时不匹配情况中恢复。 这种方法允许传统的“位选择”钳位通过“有线或”PFET上拉晶体管主动地控制“局部选择”。 单独的读写全局“位线”对可以独立优化读写性能。
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公开(公告)号：US08233331B2
公开(公告)日：2012-07-31
申请号：US12792475
申请日：2010-06-02
IPC分类号： G11C7/06
CPC分类号： H03K19/20
摘要： A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.
摘要翻译： 用于比较第一数据字与第二数据字的比较电路包括多个子电路，每个子电路具有两位静态比较级和动态复合逻辑级; 响应于子电路的相应输出的动态比较节点; 以及输出锁存器，其根据动态比较节点的逻辑状态捕获比较结果。 在示例性实施例中，本地时钟发生器提供单个控制时钟信号，用于对输出锁存器进行计时，动态比较节点的预充电以及子电路的动态复合逻辑级的计时。
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公开(公告)号：US07293209B2
公开(公告)日：2007-11-06
申请号：US11054311
申请日：2005-02-09
申请人： Yuen H. Chan , Ryan T. Freese , Antonio R. Pelella
发明人： Yuen H. Chan , Ryan T. Freese , Antonio R. Pelella
IPC分类号： G01R31/28
CPC分类号： G01R31/318552
摘要： A programmable delay circuit that delays the C2 clock signal by a variable amount that allows the output from the L1 latch to be captured even when there is a large delta between the L1 latch and its L2 latch. This allows the C2 signal to be adjusted within the system dependent upon the amount of cycle steal is needed. The C2 clock delay is inhibited during scan operation to prevent glitches and the trailing edge of the delayed C2 is controlled to maintain a constant C2 duty cycle.
摘要翻译： 一种可编程延迟电路，其将C 2时钟信号延迟可变量，即使在L 1锁存器和其L 2锁存器之间存在大的增量时，允许来自L 1锁存器的输出被捕获。 这允许在系统内调整C 2信号，这取决于所需的循环窃取量。 在扫描操作期间，C 2时钟延迟被禁止以防止毛刺，并且延迟的C 2的后沿被控制以保持恒定的C 2占空比。
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公开(公告)号：US07170774B2
公开(公告)日：2007-01-30
申请号：US11054479
申请日：2005-02-09
申请人： Yuen H. Chan , Ryan T. Freese , Antonio R. Pelella , Uma Srinivasan , Arthur D. Tuminaro , Jatinder K. Wadhwa
发明人： Yuen H. Chan , Ryan T. Freese , Antonio R. Pelella , Uma Srinivasan , Arthur D. Tuminaro , Jatinder K. Wadhwa
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C7/12 , G11C11/417
摘要： A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.
摘要翻译： 多米诺SRAM阵列恢复脉冲发生系统通过与恢复脉冲相同的本地时钟启动字解码线，从而消除了字线选择的任何种族问题。 该系统允许全局位选择（或列选择）通过释放复位信号（具有最早到达的阵列时钟ckl）来快速激活，同时保证与位解码系统几乎完美的跟踪。 这允许最广泛的写入窗口; 全局列中最早发布预充电选择，仅在位解码系统被禁用后进行复位。
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