公开(公告)号：US20080277723A1

公开(公告)日：2008-11-13

申请号：US12085669

申请日：2006-11-29

申请人： Yuji Fukui ,  Kazuhiko Yoshino ,  Satoshi Hikida ,  Shuhji Enomoto

发明人： Yuji Fukui ,  Kazuhiko Yoshino ,  Satoshi Hikida ,  Shuhji Enomoto

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7834 ,  H01L29/41783 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.

摘要翻译： 在本发明的一个实施例中，公开了具有包括元件隔离区域的小尺寸的高耐压晶体管。 半导体器件设置有形成在半导体衬底上的元件隔离区域; 由元件隔离区域划分的有源区域; 通过在其间具有栅绝缘膜而形成在有源区中的半导体衬底上的栅电极; 布置在所述半导体衬底下面的栅电极下的沟道区; 位于所述栅电极的两侧的源极区域和漏极区域; 以及位于源极区域和漏极区域之间的一个或两个以及沟道区域之间的漂移区域。 源极区域和漏极区域中的一个或两个至少部分地位于元件隔离区域上，并且通过漂移区域与沟道区域连接。

公开(公告)号：US07843014B2

公开(公告)日：2010-11-30

申请号：US12085669

申请日：2006-11-29

申请人： Yuji Fukui ,  Kazuhiko Yoshino ,  Satoshi Hikida ,  Shuhji Enomoto

发明人： Yuji Fukui ,  Kazuhiko Yoshino ,  Satoshi Hikida ,  Shuhji Enomoto

IPC分类号： H01L23/62 ,  H01L23/48

CPC分类号： H01L29/7834 ,  H01L29/41783 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.

摘要翻译： 在本发明的一个实施例中，公开了具有包括元件隔离区域的小尺寸的高耐压晶体管。 半导体器件设置有形成在半导体衬底上的元件隔离区域; 由元件隔离区域划分的有源区域; 通过在其间具有栅绝缘膜而形成在有源区中的半导体衬底上的栅电极; 布置在所述半导体衬底下面的栅电极下的沟道区; 位于所述栅电极的两侧的源极区域和漏极区域; 以及位于源极区域和漏极区域之间的一个或两个以及沟道区域之间的漂移区域。 源极区域和漏极区域中的一个或两个至少部分地位于元件隔离区域上，并且通过漂移区域与沟道区域连接。

公开(公告)号：US08466026B2

公开(公告)日：2013-06-18

申请号：US12805621

申请日：2010-08-10

申请人： Satoshi Hikida

发明人： Satoshi Hikida

IPC分类号： H01L21/8234

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0266 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device having an MOSFET serving as an element to be protected, and an electrostatic protection MOSFET element mounted on the same substrate is produced with the small number of steps while implementing a high protection ability. Low concentration regions and gate electrodes are formed and then an insulation film is formed on a whole surface. Then, etching is performed using a resist pattern as a mask to leave the insulation film in a region from a part of the gate electrode to a part of the low concentration region in each of regions A1 and A3, and on a side wall of the gate electrode in a region A2. Then, a high concentration ion implantation is performed using the gate electrodes and the insulation films as masks, and then a silicide layer is formed.

摘要翻译： 具有用作待保护元件的MOSFET和安装在同一衬底上的静电保护MOSFET元件的半导体器件在实施高保护能力的同时以少量步骤生产。 形成低浓度区域和栅电极，然后在整个表面上形成绝缘膜。 然后，使用抗蚀剂图案作为掩模进行蚀刻，以使绝缘膜在区域A1和A3的每个区域中从栅电极的一部分到低浓度区域的一部分的区域中，并且在 区域A2中的栅电极。 然后，使用栅电极和绝缘膜作为掩模进行高浓度离子注入，然后形成硅化物层。

公开(公告)号：US20120168869A1

公开(公告)日：2012-07-05

申请号：US13496436

申请日：2010-09-15

申请人： Satoshi Hikida

发明人： Satoshi Hikida

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7831

摘要： The present invention provides a high breakdown voltage transistor that eases an electric field concentration caused between a gate and a drain.The present invention provides a semiconductor device comprising: a first gate electrode formed above a semiconductor substrate through a gate insulating film; a second gate electrode that is formed above the semiconductor substrate through the gate insulating film, and that is arranged at the side of the first gate electrode through an insulating spacer; a source region and a drain region formed on the semiconductor substrate so as to sandwich the first and second gate electrodes; and an electric-field concentration easing region that is formed to sandwich some region of the semiconductor substrate below the first gate electrode, and that is formed to be overlapped with the second gate electrode and the source and drain regions.

摘要翻译： 本发明提供了一种易于在栅极和漏极之间引起的电场浓度的高击穿电压晶体管。 本发明提供一种半导体器件，包括：通过栅极绝缘膜形成在半导体衬底之上的第一栅电极; 第二栅极，其通过栅极绝缘膜形成在半导体衬底之上，并且通过绝缘间隔物布置在第一栅电极的侧面; 源极区域和漏极区域，形成在所述半导体衬底上，以夹持所述第一和第二栅电极; 以及形成为将所述半导体衬底的一部分区域夹在所述第一栅电极下方并且形成为与所述第二栅电极和所述源漏区重叠的电场浓度缓和区。

公开(公告)号：US20110042756A1

公开(公告)日：2011-02-24

申请号：US12805621

申请日：2010-08-10

申请人： Satoshi Hikida

发明人： Satoshi Hikida

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0266 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device having an MOSFET serving as an element to be protected, and an electrostatic protection MOSFET element mounted on the same substrate is produced with the small number of steps while implementing a high protection ability. Low concentration regions and gate electrodes are formed and then an insulation film is formed on a whole surface. Then, etching is performed using a resist pattern as a mask to leave the insulation film in a region from a part of the gate electrode to a part of the low concentration region in each of regions A1 and A3, and on a side wall of the gate electrode in a region A2. Then, a high concentration ion implantation is performed using the gate electrodes and the insulation films as masks, and then a silicide layer is formed.

摘要翻译： 具有用作待保护元件的MOSFET和安装在同一衬底上的静电保护MOSFET元件的半导体器件在实现高保护能力的同时以少量步骤生产。 形成低浓度区域和栅电极，然后在整个表面上形成绝缘膜。 然后，使用抗蚀剂图案作为掩模进行蚀刻，以使绝缘膜在区域A1和A3的每个区域中从栅电极的一部分到低浓度区域的一部分的区域中，并且在 区域A2中的栅电极。 然后，使用栅电极和绝缘膜作为掩模进行高浓度离子注入，然后形成硅化物层。

公开(公告)号：US5692186A

公开(公告)日：1997-11-25

申请号：US374111

申请日：1995-01-18

申请人： Toshiyuki Fukuoka ,  Satoshi Hikida

发明人： Toshiyuki Fukuoka ,  Satoshi Hikida

IPC分类号： G06N5/04 ,  G06F17/30

CPC分类号： G06N5/047 ,  Y10S707/99952

摘要： A production system including a network processing unit which allows a node, which refers to a data part which has changed, to execute a necessary change such that nodes in a data base are always kept in a latest state, and a production processing unit which selects and matches only a production rule, which refers to the node which has changed, so as to shorten the time required for the matching processing. A method of node control designates the direct node which is not necessary to be processed, when there is a change in the data part of a hierarchical network, so as to perform the processing in the network efficiently.

摘要翻译： 一种生产系统，包括网络处理单元，所述网络处理单元允许参考已经改变的数据部分的节点执行必要的改变，使得数据库中的节点总是保持在最新状态;以及生产处理单元，其选择 并且仅匹配引用已经改变的节点的生产规则，以便缩短匹配处理所需的时间。 当层次化网络的数据部分发生变化时，节点控制方法指定不需要处理的直接节点，以便有效地执行网络中的处理。

公开(公告)号：US09086812B2

公开(公告)日：2015-07-21

申请号：US13579974

申请日：2011-02-17

申请人： Haruo Yokota ,  Satoshi Hikida

发明人： Haruo Yokota ,  Satoshi Hikida

IPC分类号： G06F12/08 ,  G06F3/06 ,  G06F11/20

CPC分类号： G06F3/0625 ,  G06F3/0634 ,  G06F3/068 ,  G06F11/2071 ,  Y02D10/154

摘要： A storage device has plural data disks including a primary data area and a backup data area. Performance and reliability are secured while conserving power. A system management means includes a disk rotational state detection means, a disk rotational state control means for rotating or stopping a data disk, and a data placement control means for accessing the data disk to move the data. The data placement control means, if the data disk of the primary or backup side has been stopped at writing time, spins up and accesses thereof, and if the data disk of the primary or backup side has been stopped at reading time, prioritizes the side that is being rotated and accesses thereto, and if the data disk of the primary and backup side have both been stopped at reading time, spins up and accesses the side that has been stopped for the longer time.

摘要翻译： 存储装置具有包括主数据区和备份数据区的多个数据盘。 在节省电力的同时保证性能和可靠性。 系统管理装置包括盘旋转状态检测装置，用于旋转或停止数据盘的盘旋转状态控制装置，以及用于访问数据盘以移动数据的数据放置控制装置。 数据放置控制手段，如果主要或备用端的数据盘在写入时已经停止，则自动上载和访问数据，并且如果在读取时间主或备用端的数据盘已经被停止，则侧面的优先级 正在旋转并访问，并且如果主和备份侧的数据盘在读取时都已经停止，则旋转并访问已经停止的时间较长的一侧。

公开(公告)号：US08241985B2

公开(公告)日：2012-08-14

申请号：US12659514

申请日：2010-03-11

申请人： Satoshi Hikida

发明人： Satoshi Hikida

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28105 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/0922

摘要： A high breakdown voltage MOS transistor capable of reducing a leakage current while reducing an element size as compared with conventional ones is realized. On a P type well, with a channel area ch in between, an N type first impurity diffusion area including a drain area and drain side drift area, and an N type second impurity diffusion area including a source area and a source side drift area are formed. Moreover, a gate electrode is formed, via a gate oxide film, above a part of the first impurity diffusion area, above the channel area and above a part of the second impurity diffusion area. The gate electrode is doped with an N type, and an impurity concentration of portions located above the first and the second impurity diffusion areas is lower than an impurity concentration of a portion located above the channel area.

摘要翻译： 能够实现与传统元件相比减小元件尺寸的能够降低漏电流的高耐压电压MOS晶体管。 在P型阱中，沟道区ch之间，包括漏极区和漏极侧漂移区的N型第一杂质扩散区域和包括源极区域和源极侧漂移区域的N型第二杂质扩散区域分别为 形成。 此外，栅电极经由栅极氧化膜形成在第一杂质扩散区的一部分上方，在沟道区上方和第二杂质扩散区的一部分之上。 栅电极被掺杂为N型，并且位于第一和第二杂质扩散区上方的部分的杂质浓度低于位于沟道区上方的部分的杂质浓度。

公开(公告)号：US20100027906A1

公开(公告)日：2010-02-04

申请号：US12458963

申请日：2009-07-28

申请人： Takayuki Hara ,  Haike Guan ,  Satoshi Hikida

发明人： Takayuki Hara ,  Haike Guan ,  Satoshi Hikida

IPC分类号： G06K9/40

CPC分类号： G06T5/002 ,  G06T5/20 ,  G06T7/13 ,  G06T2207/20012 ,  G06T2207/20192 ,  H04N1/409

摘要： An image processing unit is disclosed that smoothens a notice pixel of input image data with pixel values of pixels around the notice pixel to reduce noise in the image data. The image processing unit includes an edge extraction unit that extracts an edge based on the pixel values of the image data; a region determination unit that determines a region to be processed where a sum of edge intensities of the pixels including the notice pixel becomes greater than or equal to a threshold; and a smoothening unit that changes a smoothening intensity in accordance with a size of the region to be processed to smoothen the notice pixel corresponding to the region to be processed.

摘要翻译： 公开了一种图像处理单元，其使通知像素周围的像素的像素值平滑输入图像数据的通知像素，以减少图像数据中的噪声。 图像处理单元包括边缘提取单元，其基于图像数据的像素值提取边缘; 区域确定单元，其确定包括通知像素的像素的边缘强度之和变得大于或等于阈值的待处理区域; 以及平滑化单元，其根据要处理的区域的大小改变平滑强度，以平滑对应于待处理区域的通知像素。

公开(公告)号：US5620914A

公开(公告)日：1997-04-15

申请号：US460724

申请日：1995-06-02

申请人： Satoshi Hikida ,  Norihiro Tokuyama

发明人： Satoshi Hikida ,  Norihiro Tokuyama

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L29/4983

摘要： A method of producing a semiconductor device having a LDD structure using a semiconductor substrate laminated with an insulating film, a polysilicon layer, and a first conductive layer where the first conductive layer is formed of a high melting point metal and the first conductive layer and polysilicon layer are removed in the region other than a gate pattern formation region but without exposing the insulating layer. After implanting the semiconductor substrate with a first impurity, the residual polysilicon layer in the region other than the gate pattern formation region along with a polysilicon layer sidewall in the gate pattern formation region are converted into a silicon oxide layer by subjecting to oxidation treatment, and the semiconductor substrate is laminated with a second conductive layer. Subsequently, the second conductive layer is removed by anisotropic etching so as to remain only on the sidewall of the gate pattern formation region, and the semiconductor substrate is then implanted with a second impurity to form source and drain regions.

摘要翻译： 一种制造具有LDD结构的半导体器件的方法，该半导体器件使用层压有绝缘膜，多晶硅层和第一导电层的半导体衬底，其中第一导电层由高熔点金属形成，第一导电层和多晶硅 在除了栅极图案形成区域之外的区域中去除层，但不暴露绝缘层。 在用第一杂质注入半导体衬底之后，栅极图案形成区域中除了栅极图案形成区域以外的区域中的剩余多晶硅层与栅极图案形成区域中的多晶硅层侧壁一起通过进行氧化处理而转化为氧化硅层， 半导体衬底与第二导电层层压。 随后，通过各向异性蚀刻去除第二导电层，以仅保留在栅极图案形成区域的侧壁上，然后用第二杂质注入半导体衬底以形成源极和漏极区域。