公开(公告)号：US4995003A

公开(公告)日：1991-02-19

申请号：US289115

申请日：1988-12-23

申请人： Yuji Watanabe ,  Haruki Toda ,  Hiroshi Sahara ,  Shigeo Ohshima

发明人： Yuji Watanabe ,  Haruki Toda ,  Hiroshi Sahara ,  Shigeo Ohshima

IPC分类号： G11C11/417 ,  G06F5/08 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/41

CPC分类号： G06F5/08 ,  G11C7/1006

摘要： A data transfer circuit is connected between first and second circuits so as to control data transfers therebetween. The data transfer circuit comprises first and second latch circuits for latching data in response to first and second latch control signals, respectively, a first data transfer gate connected between the first circuit and the first latch circuit and responsive to a first gate control signal to make electrical connection or disconnection therebetween, a second transfer gate connected between the first and second data latch circuits and responsive to a second gate control signal to make electrical connection or disconnection therebetween, and a third data transfer gate connected between the second data latch circuit and the second circuit and responsive to a third gate control signal to make electrical connection or disconnection therebetween. After data is transferred from the first circuit to the first data latch circuit, the data can be transferred from the data latch circuit to the second data latch circuit even if the data in the data first circuit disappears. The third data transfer gate can be opened to transfer data from the second data latch circuit to the second circuit.

公开(公告)号：US5107464A

公开(公告)日：1992-04-21

申请号：US480902

申请日：1990-02-16

申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/846

摘要： In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defective column detection.

公开(公告)号：US4862420A

公开(公告)日：1989-08-29

申请号：US171858

申请日：1988-03-22

申请人： Haruki Toda ,  Hiroshi Sahara ,  Shigeo Ohshima

发明人： Haruki Toda ,  Hiroshi Sahara ,  Shigeo Ohshima

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/06 ,  G11C8/18 ,  G11C11/401 ,  G11C11/409

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/103 ,  G11C8/06

摘要： A semiconductor memory device determines the level of a select control signal, according to the level of drive signals for two systems as generated in the preceding access cycle, and the level of the least significant bit of an address to fetch data in a desired serial access cycle. In accordance with this select signal, a select circuit selects one of the drive signals as generated by drive signal generating circuits, and supplies the selected signal to two data selecting/fetching systems. The function of this select circuit allows one of the two data selecting/fetching systems to first start the data access operation.

公开(公告)号：US4678934A

公开(公告)日：1987-07-07

申请号：US884629

申请日：1986-07-11

申请人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

发明人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

IPC分类号： G11C11/40 ,  G11C8/06 ,  H03K3/356 ,  H03K3/26 ,  G11C7/00 ,  H03K17/687 ,  H03K19/094

CPC分类号： H03K3/356026 ,  G11C8/06

摘要： A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor, having a current path connected between the gate of the first MOS transistor and the first output terminal and a gate connected to the first output terminal, for charging the gate of the first MOS transistor when the gate potential of the first MOS transistor is dropped a predetermined level in comparison with that of the first output terminal.

摘要翻译： 触发器电路具有设置在5V的电源端子，第一和第二输出端子，用于将第一和第二端子中的一个充电至5V并将第一和第二端子中的另一个放电至0V的锁存部分 根据输入信号，具有连接在电源和第一输出端子之间的电流路径的第一MOS晶体管，第二MOS晶体管，用于对第一MOS晶体管的栅极充电，同时第二输出端子的电位从5V变为 0V，以及用于自举第一MOS晶体管的栅极电位以使第一MOS晶体管导通的电容器。 触发器电路还包括第三MOS晶体管，其具有连接在第一MOS晶体管的栅极和第一输出端子之间的电流路径和连接到第一输出端子的栅极，用于对第一MOS晶体管的栅极充电， 与第一输出端子相比，第一MOS晶体管的栅极电位下降到预定水平。

公开(公告)号：US4794569A

公开(公告)日：1988-12-27

申请号：US863190

申请日：1986-05-14

申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

IPC分类号： G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C11/4096 ,  G11C11/4094

摘要： In this invention, in a sensing circuit of a dynamic memory, barrier transistors are provided between the bit lines and the sensing amplifier. A circuit is provided that, on sensing and on data transfer, changes the gate potential of the barrier transistors so that during the sensing operation the barrier transistors are temporarily turned OFF, so that sensing can be carried out with high sensitivity, as the sensing system is not affected by the parasitic capacitance of the bit lines, while, on data transfer to the input/output lines, the gate potential of the barrier transistors is raised to a level greater than a value reached by adding the threshold value of the MOS transistors to the power source voltage, so that the conductance of the barrier transistors is increased, thereby speeding up the presensing of the input/output lines in the sensing circuit.

摘要翻译： 在本发明中，在动态存储器的感测电路中，在位线和感测放大器之间设置有阻挡晶体管。 提供了一种电路，其在感测和数据传输时改变势垒晶体管的栅极电位，使得在感测操作期间，阻挡晶体管暂时断开，使得可以以高灵敏度进行感测，作为感测系统 不受位线的寄生电容的影响，而在向输入/输出线路传输数据时，势垒晶体管的栅极电位升高到大于通过将MOS晶体管的阈值相加而达到的值 以使得阻挡晶体管的电导增加，从而加速感测电路中的输入/输出线的预置。

公开(公告)号：US5237532A

公开(公告)日：1993-08-17

申请号：US794668

申请日：1991-11-18

申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

IPC分类号： G11C7/10

CPC分类号： G11C7/103

摘要： In a semiconductor memory having a column-direction serial access function, two systems of circuits for selecting and fetching data are provided. A circuit operation is alternately performed such that one system is set up while the other system is accessed, thereby reducing a cycle time for a data selecting/fetching operation.

摘要翻译： 在具有列方向串行访问功能的半导体存储器中，提供用于选择和取出数据的两个电路系统。 交替执行电路操作，使得在另一个系统被访问时建立一个系统，从而减少数据选择/取出操作的周期时间。

公开(公告)号：US5075887A

公开(公告)日：1991-12-24

申请号：US647202

申请日：1991-01-28

申请人： Koichi Magome ,  Masakazu Kiryu ,  Shigeo Ohshima ,  Haruki Toda ,  Hiroshi Sahara

发明人： Koichi Magome ,  Masakazu Kiryu ,  Shigeo Ohshima ,  Haruki Toda ,  Hiroshi Sahara

IPC分类号： G11C7/00 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/409

CPC分类号： G11C7/20 ,  G11C11/4072 ,  G11C11/409 ,  G11C7/00

摘要： A semiconductor memory device is disclosed which comprises, as shown in FIG. 1, a pair of column lines, memory cells connected to the corresponding column lines, a sense amplifier connected to the column lines, row lines for selecting the memory cells in accordance with a row address signal, and first and second transistors having their current paths connected between the column lines and a fixed potential supply terminal supplied with a positive power source potential or a ground potential, wherein the gates of the first and second transistors are connected to the first and second row lines for a data rewrite operation which can be selected independently of the row line.

公开(公告)号：US5051954A

公开(公告)日：1991-09-24

申请号：US406420

申请日：1989-09-11

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/10

CPC分类号： G11C11/4097 ,  G11C11/408 ,  G11C11/4096

摘要： Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.

公开(公告)号：US5084635A

公开(公告)日：1992-01-28

申请号：US588809

申请日：1990-09-27

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： H03K19/20 ,  G06F15/78 ,  G06F17/50 ,  G11C7/10 ,  G11C11/401

CPC分类号： G11C7/1075 ,  G11C7/1015

摘要： A function selection circuit includes a first signal generating circuit for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.

公开(公告)号：US5007028A

公开(公告)日：1991-04-09

申请号：US552851

申请日：1990-07-16

申请人： Shigeo Ohshima ,  Haruki Toda ,  Tatsuo Ikawa

发明人： Shigeo Ohshima ,  Haruki Toda ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407

CPC分类号： G11C7/1075

摘要： This invention provides a multiport memory including a storage section A having bit lines BL and BL, a word line WL, a data transfer gate .phi.DT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate .phi.DT.