公开(公告)号：US5892247A

公开(公告)日：1999-04-06

申请号：US546757

申请日：1995-10-23

申请人： Yukihito Oowaki ,  Mitsuhiro Noguchi ,  Tohru Maruyama

发明人： Yukihito Oowaki ,  Mitsuhiro Noguchi ,  Tohru Maruyama

IPC分类号： H01L21/18 ,  H01L21/285 ,  H01L21/335 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/778 ,  H01L29/788 ,  H01L31/0328

CPC分类号： B82Y10/00 ,  H01L21/28587 ,  H01L29/4232 ,  H01L29/66075 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66977 ,  H01L29/7606 ,  H01L29/7613 ,  H01L29/7787 ,  H01L29/7883

摘要： The semiconductor device comprises a substrate, a first conductive layer formed on the substrate with a first insulating layer inserted therebetween, thereby to constitute a first gate electrode, a second conductive layer selectively formed on the first gate electrode with a second insulating layer inserted therebetween, and a third conductive layer formed on the first and second conductive layer, thereby to constitute first and second electrodes respectively connected to the first and second conductive layers.

摘要翻译： 半导体器件包括衬底，形成在衬底上的第一绝缘层的第一导电层，从而构成第一栅电极，第二导电层选择性地形成在第一栅电极上，第二绝缘层插入其间， 以及形成在第一和第二导电层上的第三导电层，从而构成分别连接到第一和第二导电层的第一和第二电极。

公开(公告)号：US07303965B2

公开(公告)日：2007-12-04

申请号：US09879208

申请日：2001-06-13

申请人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

发明人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

IPC分类号： H01L21/33 ,  H01L21/3205 ,  H01L31/00

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.

摘要翻译： 在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面 漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。 在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜 的高介电膜和栅电极。 或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。 因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

公开(公告)号：US06278165B1

公开(公告)日：2001-08-21

申请号：US09340149

申请日：1999-06-28

申请人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

发明人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.

摘要翻译： 在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面 漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。 在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜 的高介电膜和栅电极。 或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。 因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

公开(公告)号：US6040610A

公开(公告)日：2000-03-21

申请号：US56632

申请日：1998-04-08

申请人： Mitsuhiro Noguchi ,  Yukihito Oowaki

发明人： Mitsuhiro Noguchi ,  Yukihito Oowaki

IPC分类号： H01L27/04 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H03K19/0944 ,  H01L29/72

CPC分类号： H01L27/092 ,  H01L21/8238 ,  H03K19/0027

摘要： A semiconductor device comprises a chip including a MISFET having a source and a drain, in which one of the source and the drain is connected to a second current supply node, an impedance element having a first terminal connected to the other of the source and the drain and a second terminal connected to a first current supply node, and a switching element, in which a well or a body electrode of the MISFET has an active state and a standby state, and is connected to a bias voltage generator for generating different voltages through the switching element, the threshold voltage V.sub.ths during standby state of the MISFET is higher than the threshold voltage V.sub.tha during active state of the MISFET, a voltage applied to a gate of the MISFET being able to take two stationary values, and the following relationship is satisfied V.sub.DD (1-V.sub.ths /V.sub.DD)

摘要翻译： 半导体器件包括芯片，其包括具有源极和漏极的MISFET，源极和漏极中的一个连接到第二电流源节点，阻抗元件具有连接到源极的另一个的第一端子和 漏极和连接到第一电流源节点的第二端子，以及开关元件，其中MISFET的阱或体电极具有活动状态和待机状态，并且连接到用于产生不同电压的偏置电压发生器 通过开关元件，MISFET的待机状态期间的阈值电压Vths高于MISFET的有效状态期间的阈值电压Vtha，施加到MISFET的栅极的电压能够采取两个稳定值，并且具有以下关系 满足VDD（1-Vths / VDD）

公开(公告)号：US06690047B2

公开(公告)日：2004-02-10

申请号：US10132175

申请日：2002-04-26

申请人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

发明人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.

摘要翻译： 在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面 漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。 在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜 的高介电膜和栅电极。 或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。 因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

公开(公告)号：US06323525B1

公开(公告)日：2001-11-27

申请号：US09154044

申请日：1998-09-16

申请人： Mitsuhiro Noguchi ,  Yukihito Oowaki

发明人： Mitsuhiro Noguchi ,  Yukihito Oowaki

IPC分类号： H01L2976

CPC分类号： H01L29/66477 ,  H01L21/223 ,  H01L21/2252 ,  H01L21/2253 ,  H01L21/2257 ,  H01L21/28114 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/456 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78621 ,  H01L2029/7863

摘要： A semiconductor device having a MISFET with an EV source/drain structure has a gate electrode formed on part of a first p-type semiconductor layer via a gate insulating film. A second n+-type semiconductor layer is formed in the prospective source and drain regions of the first semiconductor layer via the gate electrode, and a third n−-type semiconductor layer is formed on the second semiconductor layer. Each of source and drain regions is formed from the second and third semiconductor layers. The upper edge of the source/drain regions is formed above the boundary between the first semiconductor layer and the gate insulating film. In an ON state, part of a depletion layer in the drain region is formed in the third semiconductor layer, and part of a depletion layer in the source region is formed in the second semiconductor layer.

摘要翻译： 具有具有EV源极/漏极结构的MISFET的半导体器件具有通过栅极绝缘膜形成在第一p型半导体层的一部分上的栅电极。 在第一半导体层的前视源极和漏极区经由栅电极形成第二n +型半导体层，在第二半导体层上形成第三n型半导体层。 源极和漏极区域由第二和第三半导体层形成。 源极/漏极区的上边缘形成在第一半导体层和栅极绝缘膜之间的边界之上。 在导通状态下，在第三半导体层中形成漏极区的耗尽层的一部分，在第二半导体层中形成源极区的耗尽层的一部分。

公开(公告)号：US20060271799A1

公开(公告)日：2006-11-30

申请号：US11216018

申请日：2005-09-01

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： According to the present invention, there is provided a semiconductor device comprising: a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level, wherein said power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号 电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平，其中所述电源电路基于施加到其的第二控制信号输出具有第二电平的内部电源电压 。

公开(公告)号：US07057917B2

公开(公告)日：2006-06-06

申请号：US10743906

申请日：2003-12-24

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器，以及插在开关晶体管和读出放大器之间的晶体管。 作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值 电压和比较放大。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US06643162B2

公开(公告)日：2003-11-04

申请号：US09799694

申请日：2001-03-07

申请人： Yoshiaki Takeuchi ,  Yukihito Oowaki

发明人： Yoshiaki Takeuchi ,  Yukihito Oowaki

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.

摘要翻译： 铁电存储器具有具有铁电电容器的存储单元阵列，其被分成多个块，设置在存储单元阵列的每个块中的升压功率电路，以产生存储器的操作所需的升压电压， 升压电源开关，其设置在连接到外部电源端子的电力线与每个升压电力电路的电源端子之间，并且在正常操作期间保持ON;电压检测器电路，用于检测电力线的电压水平的下降 以及开关控制电路，用于响应于电压检测器电路，关闭当前选择的块中除了升压功率开关之外的存储单元阵列的块中的升压功率开关。

公开(公告)号：US06545323B2

公开(公告)日：2003-04-08

申请号：US10014662

申请日：2001-12-14

申请人： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

发明人： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

IPC分类号： H01L2976

CPC分类号： G11C11/4091 ,  H01L27/10897 ,  H01L27/12

摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

摘要翻译： 半导体器件包括用作形成在绝缘膜上的衬底的半导体层，布置在半导体层上并且各自具有栅极，源极和漏极的多个MOS晶体管，多个MOS的一对MOS晶体管 构成检测电路的晶体管，用于检测施加到栅极的电位的大小，作为一对晶体管的电导率差，以及与半导体层的导电类型相同的导电类型的扩散层区域，布置在源的一部分 以及构成检测电路的一对MOS晶体管的漏极，用于将用作一对MOS晶体管的基板的部分彼此连接。