公开(公告)号：US5892247A

公开(公告)日：1999-04-06

申请号：US546757

申请日：1995-10-23

申请人： Yukihito Oowaki ,  Mitsuhiro Noguchi ,  Tohru Maruyama

发明人： Yukihito Oowaki ,  Mitsuhiro Noguchi ,  Tohru Maruyama

IPC分类号： H01L21/18 ,  H01L21/285 ,  H01L21/335 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/778 ,  H01L29/788 ,  H01L31/0328

CPC分类号： B82Y10/00 ,  H01L21/28587 ,  H01L29/4232 ,  H01L29/66075 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66977 ,  H01L29/7606 ,  H01L29/7613 ,  H01L29/7787 ,  H01L29/7883

摘要： The semiconductor device comprises a substrate, a first conductive layer formed on the substrate with a first insulating layer inserted therebetween, thereby to constitute a first gate electrode, a second conductive layer selectively formed on the first gate electrode with a second insulating layer inserted therebetween, and a third conductive layer formed on the first and second conductive layer, thereby to constitute first and second electrodes respectively connected to the first and second conductive layers.

摘要翻译： 半导体器件包括衬底，形成在衬底上的第一绝缘层的第一导电层，从而构成第一栅电极，第二导电层选择性地形成在第一栅电极上，第二绝缘层插入其间， 以及形成在第一和第二导电层上的第三导电层，从而构成分别连接到第一和第二导电层的第一和第二电极。

公开(公告)号：US07303965B2

公开(公告)日：2007-12-04

申请号：US09879208

申请日：2001-06-13

申请人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

发明人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

IPC分类号： H01L21/33 ,  H01L21/3205 ,  H01L31/00

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.

摘要翻译： 在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面 漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。 在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜 的高介电膜和栅电极。 或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。 因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

公开(公告)号：US06278165B1

公开(公告)日：2001-08-21

申请号：US09340149

申请日：1999-06-28

申请人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

发明人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.

摘要翻译： 在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面 漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。 在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜 的高介电膜和栅电极。 或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。 因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

公开(公告)号：US6040610A

公开(公告)日：2000-03-21

申请号：US56632

申请日：1998-04-08

申请人： Mitsuhiro Noguchi ,  Yukihito Oowaki

发明人： Mitsuhiro Noguchi ,  Yukihito Oowaki

IPC分类号： H01L27/04 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H03K19/0944 ,  H01L29/72

CPC分类号： H01L27/092 ,  H01L21/8238 ,  H03K19/0027

摘要： A semiconductor device comprises a chip including a MISFET having a source and a drain, in which one of the source and the drain is connected to a second current supply node, an impedance element having a first terminal connected to the other of the source and the drain and a second terminal connected to a first current supply node, and a switching element, in which a well or a body electrode of the MISFET has an active state and a standby state, and is connected to a bias voltage generator for generating different voltages through the switching element, the threshold voltage V.sub.ths during standby state of the MISFET is higher than the threshold voltage V.sub.tha during active state of the MISFET, a voltage applied to a gate of the MISFET being able to take two stationary values, and the following relationship is satisfied V.sub.DD (1-V.sub.ths /V.sub.DD)

摘要翻译： 半导体器件包括芯片，其包括具有源极和漏极的MISFET，源极和漏极中的一个连接到第二电流源节点，阻抗元件具有连接到源极的另一个的第一端子和 漏极和连接到第一电流源节点的第二端子，以及开关元件，其中MISFET的阱或体电极具有活动状态和待机状态，并且连接到用于产生不同电压的偏置电压发生器 通过开关元件，MISFET的待机状态期间的阈值电压Vths高于MISFET的有效状态期间的阈值电压Vtha，施加到MISFET的栅极的电压能够采取两个稳定值，并且具有以下关系 满足VDD（1-Vths / VDD）

公开(公告)号：US06690047B2

公开(公告)日：2004-02-10

申请号：US10132175

申请日：2002-04-26

申请人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

发明人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.

摘要翻译： 在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面 漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。 在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜 的高介电膜和栅电极。 或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。 因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

公开(公告)号：US06323525B1

公开(公告)日：2001-11-27

申请号：US09154044

申请日：1998-09-16

申请人： Mitsuhiro Noguchi ,  Yukihito Oowaki

发明人： Mitsuhiro Noguchi ,  Yukihito Oowaki

IPC分类号： H01L2976

CPC分类号： H01L29/66477 ,  H01L21/223 ,  H01L21/2252 ,  H01L21/2253 ,  H01L21/2257 ,  H01L21/28114 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/456 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78621 ,  H01L2029/7863

摘要： A semiconductor device having a MISFET with an EV source/drain structure has a gate electrode formed on part of a first p-type semiconductor layer via a gate insulating film. A second n+-type semiconductor layer is formed in the prospective source and drain regions of the first semiconductor layer via the gate electrode, and a third n−-type semiconductor layer is formed on the second semiconductor layer. Each of source and drain regions is formed from the second and third semiconductor layers. The upper edge of the source/drain regions is formed above the boundary between the first semiconductor layer and the gate insulating film. In an ON state, part of a depletion layer in the drain region is formed in the third semiconductor layer, and part of a depletion layer in the source region is formed in the second semiconductor layer.

摘要翻译： 具有具有EV源极/漏极结构的MISFET的半导体器件具有通过栅极绝缘膜形成在第一p型半导体层的一部分上的栅电极。 在第一半导体层的前视源极和漏极区经由栅电极形成第二n +型半导体层，在第二半导体层上形成第三n型半导体层。 源极和漏极区域由第二和第三半导体层形成。 源极/漏极区的上边缘形成在第一半导体层和栅极绝缘膜之间的边界之上。 在导通状态下，在第三半导体层中形成漏极区的耗尽层的一部分，在第二半导体层中形成源极区的耗尽层的一部分。

公开(公告)号：US08395922B2

公开(公告)日：2013-03-12

申请号：US13035134

申请日：2011-02-25

申请人： Mitsuhiro Noguchi ,  Kenji Sawamura ,  Takeshi Kamigaichi ,  Katsuaki Isobe

发明人： Mitsuhiro Noguchi ,  Kenji Sawamura ,  Takeshi Kamigaichi ,  Katsuaki Isobe

IPC分类号： G11C5/06

CPC分类号： G11C5/025 ,  G11C16/0483 ,  G11C16/26

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal. At least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction is set smaller than each of the plurality of first interconnects, and the first sense amplifier circuit and the second sense amplifier circuit are disposed to face each other across the memory cell array.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，第一读出放大器电路和第二读出放大器电路。 存储单元阵列包括多个第一存储单元单元，多个第二存储单元单元，多个第一互连和多个第二互连。 第一读出放大器电路连接到多个第一互连。 第二读出放大器电路连接到多个第二互连。 互连上表面的高度相等。 沿着与第一方向垂直的第二方向的多个第二互连件的每一个的宽度中的至少一个以及沿着垂直于第一方向和第二方向的第三方向的多个第二互连件中的每一个的厚度被设置得较小 并且第一读出放大器电路和第二读出放大器电路被设置为跨越存储单元阵列彼此面对。

公开(公告)号：US08327229B2

公开(公告)日：2012-12-04

申请号：US12818709

申请日：2010-06-18

申请人： Mitsuhiro Noguchi

发明人： Mitsuhiro Noguchi

IPC分类号： G11C29/00

CPC分类号： G11C16/3427 ,  G06F11/1068 ,  G11C7/1006 ,  G11C8/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C19/00 ,  G11C29/00

摘要： A data memory system is provided which includes a nonvolatile memory cell array, an error correction code generation circuit, an error correction code decoding circuit, and a first circuit. The nonvolatile memory cell array includes a plurality of memory cells which store digital data each having at least a value of “1” or “0” as a charge of a charge accumulation layer included in each memory cell, and use a difference between charges of the accumulation layer as a writing bit or an erasing bit. The nonvolatile memory cell array erases memory cells in units of pages, each page being formed of adjacent memory cells included in the plurality of memory cells.

摘要翻译： 提供一种包括非易失性存储单元阵列，纠错码产生电路，纠错码解码电路和第一电路的数据存储系统。 非易失性存储单元阵列包括多个存储单元，其存储每个具有至少1或0值的数字数据作为每个存储单元中包含的电荷累积层的电荷，并且使用积累层的电荷之间的差作为 写位或擦除位。 非易失性存储单元阵列以页为单位擦除存储单元，每页由包含在多个存储单元中的相邻存储单元形成。

公开(公告)号：US08185802B2

公开(公告)日：2012-05-22

申请号：US12369889

申请日：2009-02-12

申请人： Mitsuhiro Noguchi

发明人： Mitsuhiro Noguchi

IPC分类号： G11C29/00

CPC分类号： G11C16/3427 ,  G06F11/1068 ,  G11C7/1006 ,  G11C8/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C19/00 ,  G11C29/00

摘要： A data memory system includes a nonvolatile memory cell array which includes a plurality of memory cells, a page adjacently formed by the plurality of memory cells being collectively erased in the nonvolatile memory cell, at least binary pieces of digital data of “1” and “0” being stored as charges of a charge accumulation layer in the memory cell, a programming bit and an erasing bit being formed by a difference between the charges of the charge accumulation layer. And the system includes an error correcting code generation circuit, an error correcting code decoding circuit, and a code conversion circuit.

摘要翻译： 一种数据存储器系统包括：非易失性存储单元阵列，其包括多个存储单元，由所述多个存储器单元相邻形成的页面在所述非易失性存储单元中被共同擦除;至少二进制数字数据“1”和“ 0“作为电荷累积层的电荷存储在存储单元中，由电荷累积层的电荷之间的差异形成的编程位和擦除位。 该系统包括纠错码产生电路，纠错码解码电路和代码转换电路。

公开(公告)号：US20120037973A1

公开(公告)日：2012-02-16

申请号：US13281083

申请日：2011-10-25

申请人： Kenji GOMIKAWA ,  Tadashi Iguchi ,  Mitsuhiro Noguchi ,  Shoichi Watanabe

发明人： Kenji GOMIKAWA ,  Tadashi Iguchi ,  Mitsuhiro Noguchi ,  Shoichi Watanabe

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

摘要翻译： 存储单元包括浮置栅电极，第一电极间绝缘膜和控制栅电极。 外围晶体管包括下电极，第二电极间绝缘膜和上电极。 下电极和上电极通过设置在第二电极间绝缘膜上的开口电连接。 第一和第二电极间绝缘膜包括高电容率材料，第一电极间绝缘膜具有第一结构，第二电极间绝缘膜具有与第一结构不同的第二结构。