公开(公告)号：US6088819A

公开(公告)日：2000-07-11

申请号：US910221

申请日：1997-08-13

申请人： Yukinobu Adachi ,  Hiromi Okimoto ,  Masanori Hayashikoshi

发明人： Yukinobu Adachi ,  Hiromi Okimoto ,  Masanori Hayashikoshi

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C11/401 ,  G11C11/407 ,  G11C29/14 ,  G11C29/50 ,  H01L21/822 ,  H01L27/04 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C11/401

摘要： In a DRAM, a boosted voltage Vpp is applied to a selected word line WL1 in a normal mode. In a test mode, a power supply voltage Vcc at a level lower than Vpp level is applied onto selected word line WL1. High data written into memory cell in the test mode of the DRAM is at the level lower than that of the high data written into memory cell in the normal mode. Therefore, a time before an H.fwdarw.L error occurs can be reduced, and a test time can be reduced.

摘要翻译： 在DRAM中，升压电压Vpp以正常模式施加到所选字线WL1。 在测试模式中，将低于Vpp电平的电源电压Vcc施加到所选字线WL1上。 在DRAM的测试模式下写入存储单元的高数据处于正常模式下写入存储单元的高数据的数据级。 因此，可以减少发生H-> L误差之前的时间，并且可以减少测试时间。

公开(公告)号：US5416366A

公开(公告)日：1995-05-16

申请号：US971186

申请日：1992-11-03

申请人： Yukinobu Adachi

发明人： Yukinobu Adachi

IPC分类号： H03K17/14 ,  H03K19/003 ,  H03K19/0948

CPC分类号： H03K19/00384 ,  H03K17/145

摘要： Fluctuation of the minimum voltage value allowing determination of the "H" level of an input signal and of maximum voltage value allowing determination of the "L" level of the input signal dependent on the supply voltage is suppressed, in order to enlarge operation margin. A semiconductor integrated circuit device includes a P channel transistor and an N channel transistor constituting a CMOS inverter, an N channel transistor connected in parallel to N channel transistor, and a plurality of N channel transistors for applying a voltage provided by lowering the supply voltage to the gate electrode of N channel transistor, in which a plurality of N channel transistor are connected in series.

摘要翻译： 抑制了允许确定输入信号的“H”电平的最小电压值的波动和允许根据电源电压确定输入信号的“L”电平的最大电压值，以便放大操作余量。 半导体集成电路器件包括P沟道晶体管和构成CMOS反相器的N沟道晶体管，N沟道晶体管并联连接到N沟道晶体管，以及多个N沟道晶体管，用于将通过降低电源电压而提供的电压施加到 N沟道晶体管的栅电极，其中多个N沟道晶体管串联连接。

公开(公告)号：US20080286463A1

公开(公告)日：2008-11-20

申请号：US12040298

申请日：2008-02-29

申请人： ROBIN L. TINER ,  Gaku Furuta ,  Yukinobu Adachi

发明人： ROBIN L. TINER ,  Gaku Furuta ,  Yukinobu Adachi

IPC分类号： C23C16/453

CPC分类号： H01J37/32082 ,  H01J37/32623 ,  H01J37/32651 ,  H01J2237/0206

摘要： The present invention generally comprises an RF shutter assembly for use in a plasma processing apparatus. The RF shutter assembly may reduce the amount of plasma creep below the substrate and shadow frame during processing, thereby reducing the amount of deposition that occurs on undesired surfaces. By reducing the amount of deposition on undesired surfaces, particle flaking and thus, substrate contamination may be reduced.

摘要翻译： 本发明通常包括用于等离子体处理装置的RF快门组件。 RF快门组件可以在处理期间减少基板和阴影框架下方的等离子体蠕变的量，从而减少在不期望的表面上发生的沉积量。 通过减少不期望的表面上的沉积量，可能会降低颗粒剥落，从而可能降低底物污染。

公开(公告)号：US08281739B2

公开(公告)日：2012-10-09

申请号：US12040298

申请日：2008-02-29

申请人： Robin L. Tiner ,  Gaku Furuta ,  Yukinobu Adachi

发明人： Robin L. Tiner ,  Gaku Furuta ,  Yukinobu Adachi

IPC分类号： C23C16/00 ,  H01L21/00

CPC分类号： H01J37/32082 ,  H01J37/32623 ,  H01J37/32651 ,  H01J2237/0206

摘要： The present invention generally comprises an RF shutter assembly for use in a plasma processing apparatus. The RF shutter assembly may reduce the amount of plasma creep below the substrate and shadow frame during processing, thereby reducing the amount of deposition that occurs on undesired surfaces. By reducing the amount of deposition on undesired surfaces, particle flaking and thus, substrate contamination may be reduced.

摘要翻译： 本发明通常包括用于等离子体处理装置的RF快门组件。 RF快门组件可以在处理期间减少基板和阴影框架下方的等离子体蠕变的量，从而减少在不期望的表面上发生的沉积量。 通过减少不期望的表面上的沉积量，可能会降低颗粒剥落，从而可能降低底物污染。

公开(公告)号：US5400290A

公开(公告)日：1995-03-21

申请号：US141002

申请日：1993-10-26

申请人： Katsuhiro Suma ,  Masaki Tsukude ,  Yukinobu Adachi

发明人： Katsuhiro Suma ,  Masaki Tsukude ,  Yukinobu Adachi

IPC分类号： G01R31/28 ,  G01R19/165 ,  G01R31/3185 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/46 ,  G11C29/50 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C8/00

CPC分类号： G11C29/028 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C11/401 ,  G11C2029/5004

摘要： In response to an external control signal, a first timing detecting circuit and a high voltage detecting circuit detect setting of a signature mode and provide a signature mode signal to a second timing detecting circuit. The second timing detecting circuit outputs an output buffer activating signal to the output buffer in response to the external control signal. In response to the output buffer activating signal, the output buffer detects an internal supply voltage and provides the same to an external pin.

摘要翻译： 响应于外部控制信号，第一定时检测电路和高电压检测电路检测签名模式的设置，并向第二定时检测电路提供签名模式信号。 第二定时检测电路响应外部控制信号向输出缓冲器输出输出缓冲器激活信号。 响应于输出缓冲器激活信号，输出缓冲器检测内部电源电压并将其提供给外部引脚。

公开(公告)号：US5631867A

公开(公告)日：1997-05-20

申请号：US456328

申请日：1995-06-01

申请人： Hiroshi Akamatsu ,  Yukinobu Adachi ,  Susumu Tanida ,  Tooru Ichimura

发明人： Hiroshi Akamatsu ,  Yukinobu Adachi ,  Susumu Tanida ,  Tooru Ichimura

IPC分类号： G11C11/407 ,  C04B28/34 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C5/145

摘要： An external power source voltage Vcc rises until it exceeds the threshold voltage Vth of an NMOS transistor diode-connected between the external power source (voltage Vcc) and an internal boosted power source (voltage Vpp), whereupon the NMOS transistor is turned on, supplying the internal boosted power source with a voltage (Vcc-Vth) until the power source voltage Vcc reaches its final value. And when the internal reset signal ZPOR expires, the internal boosted power source generating circuit is started to operate so that the internal boost source voltage Vpp is boosted to an intended level Vpp. As a result, when the power is turned on, early stabilization of the boosted power source voltage is realized in a semiconductor storage device.

摘要翻译： 外部电源电压Vcc上升直到其超过连接在外部电源（电压Vcc）和内部升压电源（电压Vpp）之间的NMOS晶体管二极管的阈值电压Vth，于是NMOS晶体管导通， 具有电压（Vcc-Vth）的内部升压电源，直到电源电压Vcc达到其最终值。 并且当内部复位信号ZPOR期满时，内部升压电源发生电路开始工作，使得内部升压电源电压Vpp升压到预期电平Vpp。 结果，当电源接通时，在半导体存储装置中实现升压电源电压的早期稳定。

公开(公告)号：US5287320A

公开(公告)日：1994-02-15

申请号：US846115

申请日：1992-03-05

申请人： Yukinobu Adachi

发明人： Yukinobu Adachi

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/413 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/34 ,  H01L23/58

CPC分类号： G11C11/4074 ,  G11C5/14 ,  H01L2924/0002

摘要： An improved DRAM includes a main circuit and an output driver circuit, respectively, energized by externally applied two power supply voltages. The DRAM includes a timing coinciding circuit for making the supply-timing of the two power supply voltages to the circuits coincided to each other. When power supply voltage only is applied, output driver circuit has a tendency to consume an excessive penetrating current in response to an unstable output signal provided from main circuit. Even though the two power supply voltages are applied in different timing, the excessive current consumption in the output driving circuit is avoided, since timing coinciding circuit simultaneously starts and ends the supply of output power supply voltages.

摘要翻译： 改进的DRAM包括分别由外部施加的两个电源电压激励的主电路和输出驱动器电路。 DRAM包括用于使电路的两个电源电压的电源定时彼此一致的定时一致电路。 当仅施加电源电压时，输出驱动电路响应于从主电路提供的不稳定的输出信号而具有消耗过大的穿透电流的趋势。 即使以不同的时刻施加了两个电源电压，由于定时重合电路同时开始并且结束输出电源电压的供给，因此避免了输出驱动电路中的过度的电流消耗。