公开(公告)号：US5361266A

公开(公告)日：1994-11-01

申请号：US138037

申请日：1993-10-19

申请人： Yukio Kodama ,  Kazuo Murakami ,  Hideo Yoshida

发明人： Yukio Kodama ,  Kazuo Murakami ,  Hideo Yoshida

IPC分类号： G11B20/18 ,  H03M13/00 ,  H03M13/29 ,  G06F11/10

CPC分类号： H03M13/091 ,  H03M13/1515 ,  H03M13/159 ,  H03M13/29 ,  H03M13/6575

摘要： An error correction circuit is capable of performing correction errors in data at a high speed. A syndrome generator (2) calculates syndromes of RS codes based on partial data streams which are given from a data buffer (1). A received CRC generator (13) performs CRC coding on the partial data streams which are given from a data buffer (1) to thereby obtain received CRCs. An error pattern CRC generator (14) calculates error pattern CRCs of the respective partial data stream based on error patterns which are generated by an error pattern generation circuit (33). Under the control of a control circuit (40), the operations performed by the syndrome generator (2), the received CRC generator (13) and the error pattern CRC generator (14) are carried out at the same time. An improvement in the speed of error correction of the partial data streams performed by the error correction means directly leads to an improvement in the speed of the whole error correction.

摘要翻译： 误差校正电路能够以高速执行数据中的校正误差。 校正子发生器（2）基于从数据缓冲器（1）给出的部分数据流来计算RS码的校验子。 接收到的CRC发生器（13）对从数据缓冲器（1）给出的部分数据流执行CRC编码，从而获得接收到的CRC。 错误模式CRC发生器（14）基于由错误模式产生电路（33）生成的错误模式来计算各部分数据流的错误模式CRC。 在控制电路（40）的控制下，由校正子发生器（2），接收到的CRC发生器（13）和错误模式CRC发生器（14）执行的操作同时进行。 由纠错装置执行的部分数据流的纠错速度的改善直接导致整个纠错的速度的提高。

公开(公告)号：US5917841A

公开(公告)日：1999-06-29

申请号：US748509

申请日：1996-11-08

申请人： Yukio Kodama ,  Kazuo Murakami

发明人： Yukio Kodama ,  Kazuo Murakami

IPC分类号： G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/09 ,  H03M13/15 ,  H04L1/00 ,  G06F11/00

CPC分类号： H03M13/09 ,  H03M13/15

摘要： A Cyclic Redundancy Check (CRC) code word except a fixed pattern is provided to a code data input terminal of a division circuit in synchronization with a clock signal and divided at the division circuit, then, a remainder data of the division result is outputted from output terminals. The remainder data outputted from the output terminals is compared with a CRC inherent value at a comparison circuit, and a comparison result signal indicating whether the CRC code word includes errors is outputted. A temporary memory means takes in the comparison result signal in response to rise of a clock signal inputted into a clock signal input terminal, temporarily stores it, then output its storage contents as an error detecting signal via an output node.

摘要翻译： 除了固定模式之外的循环冗余校验（CRC）码字被提供给与时钟信号同步的分频电路的码数据输入端，并在分频电路中分频，然后从分频电路输出除法结果的余数数据 输出端子。 将从输出端子输出的余数与比较电路的CRC固有值进行比较，并输出指示CRC码字是否包含错误的比较结果信号。 临时存储器装置响应于输入到时钟信号输入端的时钟信号的上升而接收比较结果信号，暂时存储，然后通过输出节点输出其存储内容作为错误检测信号。

公开(公告)号：US5870413A

公开(公告)日：1999-02-09

申请号：US820385

申请日：1997-03-12

申请人： Yukio Kodama ,  Kazuo Murakami

发明人： Yukio Kodama ,  Kazuo Murakami

IPC分类号： H03M13/00 ,  G06F11/10

CPC分类号： H03M13/09

摘要： When encoding, data bits in a CRC code word are received for every bit by a dividing circuit where the CRC code word is divided by a generation polynomial and a remainder is output from parallel data output terminals. The remainder is added to a CRC intrinsic value and "0" information in the adder. The addition result is a CRC code in a CRC code word for transmission. When a code error is detected, data bits in a CRC code word and a CRC code are received for every bit by the dividing circuit, where they are divided by the generation polynomial and a remainder is output from the respective parallel data terminals. The remainder data is added to the CRC intrinsic value in the adder, and the result is further processed by a logical sum circuit. The logical sum is output as a CRC flag. The present invention provides a CRC code generation circuit for generating a CRC code in a CRC code word at high speed as well as a code error detection circuit for detecting a code error in a CRC code word at high speed.

摘要翻译： 当编码时，通过分割电路为每个比特接收CRC码字中的数据比特，其中CRC码字被生成多项式除以余数由并行数据输出端输出。 其余部分加到CRC固有值，加法器中加上“0”信息。 相加结果是用于传输的CRC码字中的CRC码。 当检测到代码错误时，由分割电路为每个位接收CRC码字和CRC码中的数据位，并将其除以生成多项式，并从各个并行数据终端输出余数。 剩余数据被加到加法器中的CRC固有值，结果被逻辑和电路进一步处理。 逻辑和作为CRC标志输出。 本发明提供了一种用于以高速CRC码字生成CRC码的CRC码生成电路，以及用于以高速检测CRC码字中的码错误的码错误检测电路。

公开(公告)号：US5935269A

公开(公告)日：1999-08-10

申请号：US827061

申请日：1997-03-26

申请人： Yukio Kodama ,  Kazuo Murakami

发明人： Yukio Kodama ,  Kazuo Murakami

IPC分类号： H03M13/00

CPC分类号： H03M13/09

摘要： When encoding data received by a dividing circuit and to be included in a CRC code word, the data is divided by a generator polynomial and remainder data resulting from the division is output from a plurality of parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value and "0" information in the adder to produce a sum. The sum is a CRC code for a CRC code word to be transmitted. When detecting code errors, data from a CRC code word is received by the dividing circuit, where the data is divided by the generator polynomial, and remainder data resulting from the division is output from the respective parallel data output terminals. The remainder data is added to the CRC intrinsic value and CRC code in the adder to produce a sum, and the sum is processed by a logical sum circuit to produce a logical sum output as a CRC flag. The CRC code generation and code error detection circuit generates CRC codes to be included in CRC code words at high speed and detects errors in received CRC code words at high speed.

摘要翻译： 当对由分割电路接收并被包括在CRC码字中的数据进行编码时，由生成多项式除以数据，并且从划分电路的多个并行数据输出端输出从分频得到的余数。 剩余数据被加到CRC固有值和加法器中的“0”信息以产生和。 总和是要发送的CRC码字的CRC码。 当检测到码错误时，分频电路接收来自CRC码字的数据，其中数据被生成多项式除，并且从各个并行数据输出端子输出由除法产生的余数。 剩余数据被加到加法器中的CRC本征值和CRC码以产生和，并且由逻辑和电路处理和以产生逻辑和输出作为CRC标志。 CRC代码生成和代码错误检测电路以高速生成CRC代码字中包含的CRC代码，并以高速检测接收的CRC码字中的错误。

公开(公告)号：US5898712A

公开(公告)日：1999-04-27

申请号：US822209

申请日：1997-03-21

申请人： Yukio Kodama ,  Kazuo Murakami

发明人： Yukio Kodama ,  Kazuo Murakami

IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/09 ,  H03M13/15

CPC分类号： H03M13/15 ,  G06F11/10 ,  H03M13/09

摘要： When encoding data bits in a CRC code word and "0" information is received for every bit by a dividing circuit, the CRC code word is divided by a generation polynomial and remainder data resulting from the division is output from parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value in the adder to produce a sum. The sum is a CRC code in a CRC code word for transmission. When a code error is detected, data having a plurality of bits in a CRC code word and a CRC code are received by the dividing circuit, where they are divided by the generation polynomial and remainder data is output from the respective parallel data terminals. The remainder data is added to the CRC intrinsic value in the adder to produce a sum, and the sum is processed into a logical sum in a logical sum circuit. The logical sum is output as a CRC flag. The present invention provides a CRC code generation circuit for generating a CRC code in a CRC code word at high speed as well as a code error detection circuit for detecting a code error in a CRC code word at high speed.

摘要翻译： 当编码CRC码字中的数据比特并且通过分频电路为每个比特接收到“0”信息时，将CRC码字除以生成多项式，并且从该除法得到的余数数据从并行数据输出端输出 分频电路。 剩余数据加到加法器中的CRC本征值以产生和。 该和是用于传输的CRC码字中的CRC码。 当检测到码错误时，分频电路接收CRC码字和CRC码中的多个位的数据，并将其除以生成多项式，并从各个并行数据终端输出余数。 剩余数据被加到加法器中的CRC本征值以产生和，并且该和被处理成逻辑和电路中的逻辑和。 逻辑和作为CRC标志输出。 本发明提供了一种用于以高速CRC码字生成CRC码的CRC码生成电路，以及用于以高速检测CRC码字中的码错误的码错误检测电路。

公开(公告)号：US06516439B2

公开(公告)日：2003-02-04

申请号：US09899062

申请日：2001-07-06

申请人： Yukio Kodama ,  Takeshi Kyomoto

发明人： Yukio Kodama ,  Takeshi Kyomoto

IPC分类号： H03M1300

CPC分类号： H03M13/091 ,  H03M13/15 ,  H03M13/2703 ,  H03M13/29

摘要： An error control apparatus includes: a deinterleaver for deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes, which is to be interleaved in accordance with a predetermined interleaving order; a first cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to a coding system of the cyclic code; and a second cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to the coding system of the cyclic code simultaneously with the cyclic code check by the first cyclic code checking circuit in substantially the same time while canceling an interleave effect by the deinterleaver.

摘要翻译： 误差控制装置包括：去交织器，用于根据预定的交织顺序对由预定循环码编码的预定数量的比特进行交织的数据进行解交织; 第一循环码检查电路，用于接收解交织器的输出，并通过与循环码的编码系统相对应的检查系统对预定位数的数据进行循环码校验; 以及第二循环码检查电路，用于通过与所述循环码的编码系统相对应的检查系统对所述解交织器的输出进行接收，并对所述预定比特数的数据进行循环码校验， 第一循环码检测电路在消除交织器的交织效应的同时基本相同。

公开(公告)号：US5020626A

公开(公告)日：1991-06-04

申请号：US494078

申请日：1990-03-15

申请人： Yukio Kodama

发明人： Yukio Kodama

IPC分类号： B60K17/346 ,  B60K23/04 ,  B60K23/08

CPC分类号： B60K17/3462 ,  B60K23/0808 ,  B60K23/04 ,  B60W2510/202

摘要： A torque distribution deciding control unit and an oil hydraulic clutch having opposite disks are provided. The clutch is disposed in a power transmitting system for four-wheel drive. One of disks is operatively connected to one of side gears of a central differential through a gear train and the other of the disks is operatively connected to the other side gear of the central differential through another gear train, whereby torque is transmitted to front and rear wheels at a distribution ratio. Loads on wheels such as weights on front and rear axles are detected. The control unit operates the clutch so as to distribute the torque at a ratio in accordance with loads on both axles.

公开(公告)号：US4896738A

公开(公告)日：1990-01-30

申请号：US63173

申请日：1987-06-15

申请人： Yukio Kodama

发明人： Yukio Kodama

IPC分类号： B60K17/346 ,  B60K23/04 ,  B60K23/08

CPC分类号： B60K17/3462 ,  B60K23/0808 ,  B60K23/04 ,  B60W2510/202

摘要： A torque distribution deciding control unit and an oil hydraulic clutch having opposite disks are provided. The clutch is disposed in a power transmitting system for four-wheel drive. One of disks is operatively connected to one of side gears of a central differential through a gear train and the other of the disks is operatively connected to the other side gear of the central differential through another gear train, whereby torque is transmitted to front and rear wheels at a distribution ratio. Loads on wheels such as weights on front and rear axles are detected. The control unit operates the clutch so as to distribute the torque at a ratio in accordance with loads on both axles.

摘要翻译： 提供了具有相对的盘的扭矩分配决定控制单元和油压离合器。 离合器设置在用于四轮驱动的动力传递系统中。 一个盘通过齿轮系可操作地连接到中央差速器的一个侧齿轮，另一个盘通过另一齿轮系可操作地连接到中央差速器的另一侧齿轮，由此扭矩传递到前后 轮子分配比例。 检测车轮上的负载，例如前轴和后轴上的重量。 控制单元操作离合器，以便根据两轴上的负载以一定比例将转矩分配。

公开(公告)号：US20100086370A1

公开(公告)日：2010-04-08

申请号：US12445229

申请日：2008-02-05

申请人： Ichiro Nagano ,  Taiji Kikuchi ,  Masakatsu Fujita ,  Yukio Kodama ,  Toyoaki Yasui ,  Katsunori Akiyama ,  Toshiya Watanabe ,  Chiaki Yasuda

发明人： Ichiro Nagano ,  Taiji Kikuchi ,  Masakatsu Fujita ,  Yukio Kodama ,  Toyoaki Yasui ,  Katsunori Akiyama ,  Toshiya Watanabe ,  Chiaki Yasuda

IPC分类号： B23B27/14 ,  B32B15/04 ,  B32B7/02 ,  B05D1/00 ,  B05D5/12 ,  B23D43/00

CPC分类号： B23F21/16 ,  B23F17/003 ,  C23C14/08 ,  C23C14/3414 ,  Y02P70/175 ,  Y10T407/27 ,  Y10T428/2495 ,  Y10T428/24983

摘要： Provided is a surface coating film having a high degree of hardness and an excellent oxidation-resistance, and a method of manufacturing thereof, a cutting tool and a cutting machine. In the surface coating film, an oxidation-resistance layer containing, as a main component, a complex oxide of Li and at least Al, is coated on the outer surface of a base material, direct thereonto or through the intermediary of a highly hard coating layer. Further, in a method of manufacturing a surface coating film, the base material as it is or a highly hard coating layer coated substance in which a highly hard coating layer is coated on the outer surface of the base material is supported in a hermetic container with the use of a holder arranged in the container, then a complex oxide forming target formed from an Li and at least Al as main components, is arranged in the container into which oxygen is then fed, and en electric discharge is effected between the complex oxide forming target as an anode and the holder as a cathode so as to form an oxidation-resistance layer on the outer surface of the base material or the highly hard coating layer coated substance.

摘要翻译： 本发明提供一种硬度高，耐氧化性优异的表面涂膜及其制造方法，切削工具和切割机。 在表面被覆膜中，作为主要成分含有Li和至少Al的复合氧化物的耐氧化层被涂覆在基材的外表面上，直接在其上或通过高硬度涂层 层。 此外，在表面被覆膜的制造方法中，将基材原料或其中在基材的外表面上涂覆高硬度涂层的高硬度涂层物质负载在密封容器中， 然后使用设置在容器中的保持器，然后将由Li和至少Al作为主要成分形成的复合氧化物形成靶设置在然后供给氧的容器中，并且在复合氧化物之间进行放电 形成靶作为阳极，并且保持器作为阴极，以在基材或高硬度涂层物质的外表面上形成抗氧化层。

公开(公告)号：US07226659B2

公开(公告)日：2007-06-05

申请号：US10866869

申请日：2004-06-15

申请人： Masanobu Misaki ,  Yukio Kodama ,  Yozo Nakamura ,  Yoshihiro Wada ,  Toyoaki Yasui ,  Toshirou Kobayashi ,  Katsuyasu Hananaka

发明人： Masanobu Misaki ,  Yukio Kodama ,  Yozo Nakamura ,  Yoshihiro Wada ,  Toyoaki Yasui ,  Toshirou Kobayashi ,  Katsuyasu Hananaka

IPC分类号： C23C14/06

CPC分类号： C23C14/024 ,  C23C14/0641 ,  C23C28/044 ,  C23C28/42 ,  Y10T83/04 ,  Y10T407/27 ,  Y10T428/265

摘要： A high wear resistant hard film is characterized by including a coating layer consisting of a metal nitride, which is formed on the outside surface of an object to be treated; a substrate layer consisting of a nitride of Ti or Cr, which is provided between the coating layer and the object to be treated; and an intermediate layer containing compositions of the coating layer in contact with the intermediate layer and the substrate layer, which is provided at an interface between the coating layer and the substrate layer, and a tool is provided with the film. There is provided a hard film having excellent oxidation resistance even at 1000° C. or higher and also having very high wear resistance.

摘要翻译： 高耐磨硬质膜的特征在于，在被处理物的外表面上形成由金属氮化物构成的被覆层， 由涂覆层和待处理物体之间设置的由Ti或Cr的氮化物构成的衬底层; 以及包含与涂覆层和基材层之间的界面处设置的与中间层和基材层接触的涂层的组合物的中间层和具有该膜的工具。 提供即使在1000℃以上也具有优异的耐氧化性也具有非常高的耐磨性的硬膜。