公开(公告)号：US08063313B2

公开(公告)日：2011-11-22

申请号：US12263614

申请日：2008-11-03

申请人： Yun-Jin Oh ,  Chang-Hoon Han ,  Kwang-Ryul Lee ,  Hyoung-Suk Kim

发明人： Yun-Jin Oh ,  Chang-Hoon Han ,  Kwang-Ryul Lee ,  Hyoung-Suk Kim

IPC分类号： H05K1/16 ,  H05K3/30

CPC分类号： H05K3/3452 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/15311 ,  H05K2201/09772 ,  H05K2201/09881 ,  H05K2203/0191 ,  H05K2203/049 ,  H05K2203/0577 ,  H05K2203/058 ,  H05K2203/0582 ,  H05K2203/0585 ,  H05K2203/1476 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A printed circuit board (PCB) and a semiconductor package that are configured to prevent delamination and voids. In one example embodiment, the semiconductor package includes a PCB having a base substrate on which conductive patterns are formed and which includes an interior region having a die paddle for receiving a semiconductor chip and an exterior region disposed outside the interior region. The PCB also includes a first solder resist formed on a portion of the base substrate corresponding to the interior region and a second solder resist formed on a portion of the base substrate corresponding to the exterior region. The second solder resist may also have a greater surface roughness than the surface roughness of the first solder resist.

摘要翻译： 配置为防止分层和空隙的印刷电路板（PCB）和半导体封装。 在一个示例性实施例中，半导体封装包括具有其上形成有导电图案的基底基板的PCB，其包括具有用于接收半导体芯片的管芯焊盘和设置在内部区域外部的外部区域的内部区域。 PCB还包括形成在对应于内部区域的基底基板的一部分上的第一阻焊剂和形成在对应于外部区域的基底基板的一部分上的第二阻焊剂。 第二阻焊剂也可以具有比第一阻焊剂的表面粗糙度更大的表面粗糙度。

公开(公告)号：US08664780B2

公开(公告)日：2014-03-04

申请号：US13534212

申请日：2012-06-27

申请人： Chang-Hoon Han ,  Jin-Ho Kim ,  Bo-Seong Kim ,  Yun-Jin Oh

发明人： Chang-Hoon Han ,  Jin-Ho Kim ,  Bo-Seong Kim ,  Yun-Jin Oh

IPC分类号： H01L23/29 ,  H01L29/40

CPC分类号： H01L23/3135 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a first semiconductor chip mounted to a substrate, a first encapsulant covering the first semiconductor chip and have first to fourth sidewall surfaces, and a chip stack mounted to the substrate and disposed on the first encapsulant. The chip stack includes a plurality of second semiconductor chips. A second encapsulant covers the chip stack. The second encapsulant may cover the first sidewall surface of the first encapsulant and expose the third sidewall surface of the first encapsulant.

摘要翻译： 半导体封装包括安装到衬底的第一半导体芯片，覆盖第一半导体芯片并具有第一至第四侧壁表面的第一密封剂和安装到衬底并且设置在第一密封剂上的芯片堆叠。 芯片堆叠包括多个第二半导体芯片。 第二密封剂覆盖芯片堆叠。 第二密封剂可以覆盖第一密封剂的第一侧壁表面并暴露第一密封剂的第三侧壁表面。

公开(公告)号：US20080136044A1

公开(公告)日：2008-06-12

申请号：US11982751

申请日：2007-11-05

申请人： Yun-Jin Oh

发明人： Yun-Jin Oh

IPC分类号： H01L23/538 ,  H01L21/60

CPC分类号： H01L25/0657 ,  H01L23/498 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48465 ,  H01L2224/49433 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099

摘要： Provided are a semiconductor package in which bonding pads of a semiconductor chip are electrically connected to interconnection portions by wire-bonding, and a method of manufacturing the semiconductor package. The semiconductor package includes: a substrate; an interconnection portion that is disposed on the substrate and comprises conductive patterns having a first thickness and conductive patterns having a second thickness that is smaller than the first thickness; at least one semiconductor chip that is mounted on the substrate and comprises a plurality of bonding pads; and a plurality of wires electrically connecting the conductive patterns and the bonding pads.

摘要翻译： 提供一种半导体封装，其中半导体芯片的焊盘通过引线接合电连接到互连部分，以及制造半导体封装的方法。 半导体封装包括：衬底; 互连部分，其布置在所述基板上并且包括具有第一厚度的导电图案和具有小于所述第一厚度的第二厚度的导电图案; 至少一个半导体芯片，其安装在所述基板上并且包括多个焊盘; 以及电连接导电图案和接合焊盘的多根电线。