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    LCD display visual enhancement driving circuit and method
    1.
    发明授权
    LCD display visual enhancement driving circuit and method 有权
    液晶显示器视觉增强驱动电路及方法

    公开(公告)号：US08411007B2

    公开(公告)日：2013-04-02

    申请号：US12660315

    申请日：2010-02-23

    申请人： Yung-Chih Chen ,  Yu-Chung Yang ,  Kun-Yueh Lin ,  Chun-Hsin Liu

    发明人： Yung-Chih Chen ,  Yu-Chung Yang ,  Kun-Yueh Lin ,  Chun-Hsin Liu

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3648 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2300/0814 ,  G09G2300/0852 ,  G09G2300/0876 ,  G09G2310/0251 ,  G09G2320/0242 ,  G09G2320/028

    摘要： A pixel in a liquid crystal display panel comprises a first sub-pixel area having a first sub-pixel electrode and a second sub-pixel area having a second sub-pixel electrode. Each sub-pixel electrode is associated with a capacitor. When a gate-line signal and a data voltage is provided to the pixel, the voltage level on the first sub-pixel electrode is substantially equal to or slightly higher than the voltage level on the second sub-pixel electrode and the capacitor associated with each sub-pixel electrode is charged. When the gate-line signal has entirely passed on partially passed, a circuit element causes the capacitor associated with the second sub-pixel electrode to transfer its charge to another capacitor, resulting in a reduction of the voltage level on the second sub-pixel electrode.

    摘要翻译： 液晶显示面板中的像素包括具有第一子像素电极的第一子像素区域和具有第二子像素电极的第二子像素区域。 每个子像素电极与电容器相关联。 当向像素提供栅极线信号和数据电压时，第一子像素电极上的电压电平基本上等于或略高于第二子像素电极和与每个子像素电极相关联的电容器的电压电平 子像素电极被充电。 当栅极线信号完全通过时，电路元件使与第二子像素电极相关联的电容器将其电荷转移到另一个电容器，导致第二子像素电极上的电压电平降低 。

    Shift register circuit
    3.
    发明授权
    Shift register circuit 有权
    移位寄存器电路

    公开(公告)号：US08515000B2

    公开(公告)日：2013-08-20

    申请号：US13044773

    申请日：2011-03-10

    申请人： Yu-Chung Yang ,  Yung-Chih Chen ,  Chih-Ying Lin ,  Kun-Yueh Lin

    发明人： Yu-Chung Yang ,  Yung-Chih Chen ,  Chih-Ying Lin ,  Kun-Yueh Lin

    IPC分类号： G11C19/00

    CPC分类号： G11C19/28 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/287

    摘要： A shift register circuit includes a plurality of shift registers. Each of the shift registers is configured for outputting a corresponding start-pulse signal and a corresponding driving-pulse signal. Each of the shift registers includes a pull-up circuit, a first driving circuit, a second driving circuit and a discharging circuit. The pull-up circuit is configured for charging a first node. The first driving circuit is configured for generating the corresponding start-pulse signal, and the second driving circuit is configured for generating the corresponding driving-pulse signal. The discharging circuit firstly discharges the first node before discharging an output terminal of the second driving circuit.

    摘要翻译： 移位寄存器电路包括多个移位寄存器。 每个移位寄存器被配置为输出相应的起始脉冲信号和相应的驱动脉冲信号。 每个移位寄存器包括上拉电路，第一驱动电路，第二驱动电路和放电电路。 上拉电路被配置为对第一节点进行充电。 第一驱动电路被配置为产生相应的起始脉冲信号，并且第二驱动电路被配置为产生相应的驱动脉冲信号。 在放电第二驱动电路的输出端子之前，放电电路首先对第一节点进行放电。

    LCD PANEL
    4.
    发明申请
    LCD PANEL 有权
    液晶面板

    公开(公告)号：US20120120035A1

    公开(公告)日：2012-05-17

    申请号：US13204941

    申请日：2011-08-08

    申请人： Yu-Chung YANG ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Kuo-Hua Hsu ,  Chih-Ying Lin ,  Kun-Yueh Lin

    发明人： Yu-Chung YANG ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Kuo-Hua Hsu ,  Chih-Ying Lin ,  Kun-Yueh Lin

    IPC分类号： G09G5/00 ,  G09G3/36

    CPC分类号： G09G3/3677 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2310/0205

    摘要： A LCD panel with an improved pixel array configuration is provided. The LCD panel uses a column inversion driving method to drive the data lines so as to achieve a stable common voltage. Moreover, by cross-connecting the layout traces of the wiring zone in a specified manner, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.

    摘要翻译： 提供了具有改进的像素阵列配置的LCD面板。 LCD面板使用列反转驱动方法驱动数据线，以达到稳定的公共电压。 此外，通过以指定的方式交叉连接布线区的布局迹线，从与子像素相邻的每两个栅极线输出的栅极脉冲彼此不重叠，从而可以正常显示该帧。

    Display Device with Bi-directional Shift Registers
    5.
    发明申请
    Display Device with Bi-directional Shift Registers 审中-公开
    具有双向移位寄存器的显示设备

    公开(公告)号：US20120086627A1

    公开(公告)日：2012-04-12

    申请号：US13270233

    申请日：2011-10-11

    申请人： Yung-Chih Chen ,  Kuo-Hua Hsu ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Yu-Hsi Ho

    发明人： Yung-Chih Chen ,  Kuo-Hua Hsu ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Yu-Hsi Ho

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3677 ,  G09G2300/0413 ,  G09G2310/0283 ,  G09G2310/0286

    摘要： A display device having bi-directional shift registers is disclosed. The display device includes a display panel which has N gate lines, a first set of dummy registers, a second set of dummy registers, a plurality of valid shift registers coupled between the two sets of dummy registers, and a first start pulse signal generator coupled to the first valid register for generating the first start pulse signal to the first valid register to enable the first gate line. The first valid register is coupled to the first set of dummy registers. The Nth valid register is coupled to the second set of dummy registers.

    摘要翻译： 公开了一种具有双向移位寄存器的显示装置。 显示装置包括具有N个栅极线的显示面板，第一组虚拟寄存器组，第二组虚拟寄存器，耦合在两组虚拟寄存器之间的多个有效移位寄存器，以及第一起始脉冲信号发生器 到第一有效寄存器，用于将第一起始脉冲信号产生到第一有效寄存器以使能第一栅极线。 第一个有效寄存器耦合到第一组虚拟寄存器。 第N个有效寄存器耦合到第二组虚拟寄存器。

    Bus-line arrangement in a gate driver
    6.
    发明授权
    Bus-line arrangement in a gate driver 有权
    总线排列在门驱动器中

    公开(公告)号：US09087492B2

    公开(公告)日：2015-07-21

    申请号：US13453581

    申请日：2012-04-23

    申请人： Chun Huan Chang ,  Chun-Hsin Liu ,  Kun-Yueh Lin ,  Ya-Ting Lin

    发明人： Chun Huan Chang ,  Chun-Hsin Liu ,  Kun-Yueh Lin ,  Ya-Ting Lin

    IPC分类号： G06F3/038 ,  G09G3/36 ,  G06F17/50 ,  G06F1/10

    CPC分类号： G09G3/3677 ,  G06F1/10 ,  G06F17/5077 ,  G09G2300/0426 ,  G09G2310/0205

    摘要： A method for use in a display panel is disclosed. The method includes providing M bus lines in the bus area for receiving a plurality of clock signals, M being a positive integer greater than 3; providing a plurality of signal lines to separately provide the clock signals from the M bus line to the circuit area, the circuit area configured to provide the plurality of sequential gate line signals in response to the clock signals, the plurality of signal lines including a plurality of adjacent signal-line pairs, each adjacent signal-line pair having a resistance difference, said signal lines including a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.

    摘要翻译： 公开了一种在显示面板中使用的方法。 该方法包括在总线区域中提供M个总线线路，用于接收多个时钟信号，M为大于3的正整数; 提供多条信号线，以将来自M总线的时钟信号分别提供给电路区域，电路区域被配置为响应于时钟信号提供多个顺序的栅极线信号，多个信号线包括多个 相邻的信号线对，每个相邻的信号线对具有电阻差，所述信号线包括最大电阻值和最小电阻值，并且其中M总线布置成使得所述M个总线线路中的任一个中的电阻差 相邻的信号线对小于最大电阻值和最小电阻值之间的值差。

    Display panel and gate driving circuit thereof
    7.
    发明授权
    Display panel and gate driving circuit thereof 有权
    显示面板及其栅极驱动电路

    公开(公告)号：US08890785B2

    公开(公告)日：2014-11-18

    申请号：US13449322

    申请日：2012-04-18

    申请人： Kun-Yueh Lin ,  Chun-Hsin Liu ,  Chun-Huan Chang ,  Ya-Ting Lin

    发明人： Kun-Yueh Lin ,  Chun-Hsin Liu ,  Chun-Huan Chang ,  Ya-Ting Lin

    IPC分类号： G09G3/36 ,  G09G3/20

    CPC分类号： G09G3/3659 ,  G09G3/2074 ,  G09G2310/0286

    摘要： A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.

    摘要翻译： 提供显示面板及其栅极驱动电路。 栅极驱动电路包括多个移位寄存器。 每个移位寄存器包括用于产生第一扫描信号的第一扫描信号发生器，用于产生第二扫描信号的第二扫描信号发生器，用于产生第一控制信号的第一控制单元和产生第二扫描信号的第二扫描信号的第二控制单元 控制信号。 这里，第一控制信号和第二控制信号由第一扫描信号发生器和第二扫描信号发生器共享。 基于上述，可以排除由电路共享引起的第一扫描信号和第二扫描信号的信号强度的减少，并且可以减少每个移位寄存器占用的码片区域。

    DISPLAY PANEL AND GATE DRIVING CIRCUIT THEREOF
    8.
    发明申请
    DISPLAY PANEL AND GATE DRIVING CIRCUIT THEREOF 有权
    显示面板和门驱动电路

    公开(公告)号：US20130100006A1

    公开(公告)日：2013-04-25

    申请号：US13449322

    申请日：2012-04-18

    申请人： Kun-Yueh Lin ,  Chun-Hsin Liu ,  Chun-Huan Chang ,  Ya-Ting Lin

    发明人： Kun-Yueh Lin ,  Chun-Hsin Liu ,  Chun-Huan Chang ,  Ya-Ting Lin

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3659 ,  G09G3/2074 ,  G09G2310/0286

    摘要： A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.

    摘要翻译： 提供显示面板及其栅极驱动电路。 栅极驱动电路包括多个移位寄存器。 每个移位寄存器包括用于产生第一扫描信号的第一扫描信号发生器，用于产生第二扫描信号的第二扫描信号发生器，用于产生第一控制信号的第一控制单元和产生第二扫描信号的第二扫描信号的第二控制单元 控制信号。 这里，第一控制信号和第二控制信号由第一扫描信号发生器和第二扫描信号发生器共享。 基于上述，可以排除由电路共享引起的第一扫描信号和第二扫描信号的信号强度的减少，并且可以减少每个移位寄存器占用的码片区域。

    Shift register circuit
    9.
    发明授权
    Shift register circuit 有权
    移位寄存器电路

    公开(公告)号：US08363777B2

    公开(公告)日：2013-01-29

    申请号：US13604632

    申请日：2012-09-06

    申请人： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

    发明人： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

    IPC分类号： G11C19/00

    CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00

    摘要： A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

    摘要翻译： 移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。 每个移位寄存器级包括上拉单元，上拉控制单元，输入单元，第一下拉单元，第二下拉单元和下拉控制单元。 上拉控制单元根据驱动控制电压和第一时钟产生第一控制信号。 上拉单元根据第一控制信号上拉相应的门信号。 输入单元用于根据具有与第一时钟相反的相位的第二时钟输入前一移位寄存器级的门信号以变为驱动控制电压。 下拉控制单元根据驱动控制电压产生第二控制信号。 第一和第二下拉单元根据第二控制信号分别下拉对应的门信号和第一控制信号。

    Shift register circuit
    10.
    发明授权
    Shift register circuit 有权

    公开(公告)号：US08284891B2

    公开(公告)日：2012-10-09

    申请号：US13468047

    申请日：2012-05-10

    申请人： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

    发明人： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

    IPC分类号： G11C19/00

    CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00

    摘要： A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.