公开(公告)号：US08450218B2

公开(公告)日：2013-05-28

申请号：US13338484

申请日：2011-12-28

申请人： Yunjun Ho ,  Brent Gilgen

发明人： Yunjun Ho ,  Brent Gilgen

IPC分类号： H01L21/31

CPC分类号： H01L21/02164 ,  H01L21/02222 ,  H01L21/02307 ,  H01L21/02326 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76897

摘要： A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.

摘要翻译： 形成氧化硅的方法包括在衬底上沉积含氮化硅的材料。 包含氮化硅的材料具有最高的最外面的含氮化硅的表面。 这种表面用体积至少为99.5％H 2 O的流体处理。 包含聚硅氮烷的旋涂电介质材料形成在经H2O处理的含氮化硅的表面上。 包含聚硅氮烷的旋涂电介质材料被氧化形成氧化硅。 考虑其他实现。

公开(公告)号：US20120100726A1

公开(公告)日：2012-04-26

申请号：US13338484

申请日：2011-12-28

申请人： Yunjun Ho ,  Brent Gilgen

发明人： Yunjun Ho ,  Brent Gilgen

IPC分类号： H01L21/316 ,  H01L21/3105

CPC分类号： H01L21/02164 ,  H01L21/02222 ,  H01L21/02307 ,  H01L21/02326 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76897

摘要： A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.

摘要翻译： 形成氧化硅的方法包括在衬底上沉积含氮化硅的材料。 包含氮化硅的材料具有最高的最外面的含氮化硅的表面。 用体积为至少99.5％H 2 O的流体处理该表面。 包含聚硅氮烷的旋涂电介质材料形成在经H2O处理的含氮化硅的表面上。 包含聚硅氮烷的旋涂电介质材料被氧化形成氧化硅。 考虑其他实现。

公开(公告)号：US08105956B2

公开(公告)日：2012-01-31

申请号：US12582181

申请日：2009-10-20

申请人： Yunjun Ho ,  Brent Gilgen

发明人： Yunjun Ho ,  Brent Gilgen

IPC分类号： H01L21/31

CPC分类号： H01L21/02164 ,  H01L21/02222 ,  H01L21/02307 ,  H01L21/02326 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76897

摘要： A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.

摘要翻译： 形成氧化硅的方法包括在衬底上沉积含氮化硅的材料。 包含氮化硅的材料具有最高的最外面的含氮化硅的表面。 这种表面用体积至少为99.5％H 2 O的流体处理。 包含聚硅氮烷的旋涂电介质材料形成在经H2O处理的含氮化硅的表面上。 包含聚硅氮烷的旋涂电介质材料被氧化形成氧化硅。 考虑其他实现。

公开(公告)号：US20110092061A1

公开(公告)日：2011-04-21

申请号：US12582181

申请日：2009-10-20

申请人： Yunjun Ho ,  Brent Gilgen

发明人： Yunjun Ho ,  Brent Gilgen

IPC分类号： H01L21/3105 ,  H01L21/312 ,  H01L21/8234

CPC分类号： H01L21/02164 ,  H01L21/02222 ,  H01L21/02307 ,  H01L21/02326 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76897

摘要： A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.

摘要翻译： 形成氧化硅的方法包括在衬底上沉积含氮化硅的材料。 包含氮化硅的材料具有最高的最外面的含氮化硅的表面。 这种表面用体积至少为99.5％H 2 O的流体处理。 包含聚硅氮烷的旋涂电介质材料形成在经H2O处理的含氮化硅的表面上。 包含聚硅氮烷的旋涂电介质材料被氧化形成氧化硅。 考虑其他实现。

公开(公告)号：US08461016B2

公开(公告)日：2013-06-11

申请号：US13268066

申请日：2011-10-07

申请人： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

发明人： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

IPC分类号： H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11573

摘要： A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.

摘要翻译： 形成存储器阵列和外围电路隔离的方法包括在存储器阵列电路隔离沟槽的侧壁和在半导体材料中形成的外围电路隔离沟槽的化学气相沉积包含二氧化硅的衬垫。 电介质材料流过含二氧化硅的衬垫以填充阵列隔离沟槽的剩余体积，并在至少一些外围隔离沟槽中的含二氧化硅的衬垫上形成电介质衬垫。 电介质材料在不大于约500℃的温度下进行炉退火。退火的电介质材料被快速热处理至不低于约800℃的温度。含二氧化硅的材料经快速热化学气相沉积 处理的介电材料以填充所述至少一些外围隔离沟槽的剩余体积。 公开了其它方面，包括由公开的方法产生的集成电路和独立于制造方法的集成电路。

公开(公告)号：US20130087883A1

公开(公告)日：2013-04-11

申请号：US13268066

申请日：2011-10-07

申请人： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

发明人： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

IPC分类号： H01L29/06 ,  H01L21/31

CPC分类号： H01L29/0649 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11573

摘要： A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.

摘要翻译： 形成存储器阵列和外围电路隔离的方法包括在存储器阵列电路隔离沟槽的侧壁和在半导体材料中形成的外围电路隔离沟槽的化学气相沉积包含二氧化硅的衬垫。 电介质材料流过含二氧化硅的衬垫以填充阵列隔离沟槽的剩余体积，并在至少一些外围隔离沟槽中的含二氧化硅的衬垫上形成电介质衬垫。 电介质材料在不大于约500℃的温度下进行炉退火。退火的电介质材料被快速热处理至不低于约800℃的温度。含二氧化硅的材料经快速热化学气相沉积 处理的介电材料以填充所述至少一些外围隔离沟槽的剩余体积。 公开了其它方面，包括由公开的方法产生的集成电路和独立于制造方法的集成电路。

公开(公告)号：US08030170B2

公开(公告)日：2011-10-04

申请号：US12633694

申请日：2009-12-08

申请人： Yunjun Ho ,  Matt Meyers ,  Kevin L. Beaman ,  Gregory J. Light

发明人： Yunjun Ho ,  Matt Meyers ,  Kevin L. Beaman ,  Gregory J. Light

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/28273 ,  H01L27/11521

摘要： Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500° C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700° C. to about 1000° C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another.

摘要翻译： 一些实施方案包括形成隔离结构的方法。 可以形成沟槽以延伸到半导体材料中。 可以在沟槽内形成聚硅氮烷，然后暴露于蒸汽中。 蒸汽暴露期间聚硅氮烷的最高温度可以小于或等于约500℃。蒸汽暴露可将所有聚硅氮烷转化为氧化硅。 氧化硅可以在惰性气氛下进行退火。 退火期间氧化硅的最高温度可以是约700℃至约1000℃。在一些实施例中，隔离结构用于将非易失性存储器组件彼此隔离。

公开(公告)号：US20110136319A1

公开(公告)日：2011-06-09

申请号：US12633694

申请日：2009-12-08

申请人： Yunjun Ho ,  Matt Meyers ,  Kevin L. Beaman ,  Gregory J. Light

发明人： Yunjun Ho ,  Matt Meyers ,  Kevin L. Beaman ,  Gregory J. Light

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/28273 ,  H01L27/11521

摘要： Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500° C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700° C. to about 1000° C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another.

摘要翻译： 一些实施方案包括形成隔离结构的方法。 可以形成沟槽以延伸到半导体材料中。 可以在沟槽内形成聚硅氮烷，然后暴露于蒸汽中。 蒸汽暴露期间聚硅氮烷的最高温度可以小于或等于约500℃。蒸汽暴露可将所有聚硅氮烷转化为氧化硅。 氧化硅可以在惰性气氛下进行退火。 退火期间氧化硅的最高温度可以是约700℃至约1000℃。在一些实施例中，隔离结构用于将非易失性存储器组件彼此隔离。