公开(公告)号：US08861287B2

公开(公告)日：2014-10-14

申请号：US13616609

申请日：2012-09-14

申请人： Yuui Shimizu ,  Masaru Koyanagi ,  Yasuhiro Suematsu

发明人： Yuui Shimizu ,  Masaru Koyanagi ,  Yasuhiro Suematsu

IPC分类号： G11C7/10 ,  G11C16/24 ,  H03K19/003 ,  H03K19/0175 ,  G11C16/26

CPC分类号： H03K19/017509 ,  G11C7/1057 ,  G11C16/24 ,  G11C16/26 ,  H03K19/00361

摘要： According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor.

摘要翻译： 根据实施例，接口电路设置有输出缓冲器，其基于晶体管的导通/截止操作和驱动晶体管的驱动器电路产生输出波形，并且能够独立地改变导通速度 和晶体管的截止速度。

公开(公告)号：US08736346B2

公开(公告)日：2014-05-27

申请号：US13524391

申请日：2012-06-15

申请人： Yuui Shimizu ,  Masaru Koyanagi

发明人： Yuui Shimizu ,  Masaru Koyanagi

IPC分类号： H03L5/00

摘要： According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.

摘要翻译： 根据一个实施例，电平移位电路包括彼此连接的多个电平移位单元，其中输出电压的上升沿的延迟时间与输出电压的下降沿的延迟时间不同 。 来自先前电平移位单元的输出电压的上升沿的延迟时间由下一个电平移位单元的输出电压的下降沿的延迟时间补偿，并且输出电压的下降沿的延迟时间 来自先前电平移位单元的输出电压的上升沿的延迟时间由下一个电平移位单元补偿。

公开(公告)号：US08531882B2

公开(公告)日：2013-09-10

申请号：US13159696

申请日：2011-06-14

申请人： Tomofumi Fujimura ,  Yuui Shimizu

发明人： Tomofumi Fujimura ,  Yuui Shimizu

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C29/808

摘要： A memory includes stacking chips. The chip includes a pad commonly connected to the chips and receiving an enable signal that enables access to each chip. The chip includes a chip address memory that can store a chip address. The chip includes a determining part comparing a select address to the chip address for determining whether they match each other. The chip includes a control-signal setting part setting the control signal inputted to the chip itself to be valid or invalid depending on a determination made by the determining part. The chip includes a chip-address setting part determining whether the chip address is stored in the chip address memory depending on number of fail bits. The device includes a memory controller allocating respectively different ones of the chip addresses to the chips based on the number of fail bits.

摘要翻译： 存储器包括堆叠芯片。 该芯片包括通常连接到芯片的接收器，并且接收能够接入每个芯片的使能信号。 该芯片包括可存储芯片地址的芯片地址存储器。 芯片包括将选择地址与芯片地址进行比较以确定它们是否彼此匹配的确定部分。 该芯片包括控制信号设定部，其根据由判定部作出的判定，将输入到芯片本身的控制信号设定为有效或无效。 芯片包括芯片地址设定部，根据故障位的数量来判定芯片地址是否存储在芯片地址存储器中。 该装置包括一个存储器控制器，该存储器控制器基于故障位数来分别分配不同芯片地址到芯片。

公开(公告)号：US08410811B2

公开(公告)日：2013-04-02

申请号：US13191825

申请日：2011-07-27

申请人： Yuui Shimizu

发明人： Yuui Shimizu

IPC分类号： H03K19/0175 ,  H03K19/00

CPC分类号： H03K19/018521 ,  H03K19/018585

摘要： According to one embodiment, an input circuit includes an input buffer, a control unit, a holding unit, a feedback unit. The input buffer receives a signal input from an outside. The input buffer includes a plurality of CMOS inverters connected in parallel. The plurality of CMOS inverters includes a plurality of PMOS transistors and a plurality of NMOS transistors. The control unit selects one or more PMOS transistors from the plurality of PMOS transistors so as to enter an operable state. The control unit selects one or more NMOS transistors from the plurality of NMOS transistors so as to enter an operable state. The holding unit holds a level of a signal transferred from the input buffer in synchronization with a clock signal. The holding unit outputs the held signal level. The feedback unit feeds the level of the signal output from the holding unit back to the control unit.

摘要翻译： 根据一个实施例，输入电路包括输入缓冲器，控制单元，保持单元，反馈单元。 输入缓冲器接收从外部输入的信号。 输入缓冲器包括并联连接的多个CMOS反相器。 多个CMOS反相器包括多个PMOS晶体管和多个NMOS晶体管。 控制单元从多个PMOS晶体管中选择一个或多个PMOS晶体管，以进入可操作状态。 控制单元从多个NMOS晶体管中选择一个或多个NMOS晶体管，以进入可操作状态。 保持单元保持与时钟信号同步地从输入缓冲器传送的信号的电平。 保持单元输出保持的信号电平。 反馈单元将从保持单元输出的信号的电平返回到控制单元。

公开(公告)号：US08315108B2

公开(公告)日：2012-11-20

申请号：US12884914

申请日：2010-09-17

申请人： Yuui Shimizu

发明人： Yuui Shimizu

IPC分类号： G11C7/10

CPC分类号： G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C16/28 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/5006

摘要： According to one embodiment, a differential circuit receives, as differential inputs, a readout signal read out from a semiconductor storage element and a reference voltage. An equalizing circuit controls, taking into account a state of a past input signal output from the differential circuit, the potential of the present differential signal output from the differential circuit. A sense amplifier detects a state of the differential signal output from the equalizing circuit. A state holding circuit holds a past state of the differential signal detected by the sense amplifier and supplies the state to the equalizing circuit.

摘要翻译： 根据一个实施例，差分电路作为差分输入接收从半导体存储元件读出的读出信号和参考电压。 考虑到从差分电路输出的过去输入信号的状态，均衡电路控制从差分电路输出的当前差分信号的电位。 读出放大器检测从均衡电路输出的差分信号的状态。 状态保持电路保持由读出放大器检测的差分信号的过去状态，并将该状态提供给均衡电路。

公开(公告)号：US07869265B2

公开(公告)日：2011-01-11

申请号：US12026077

申请日：2008-02-05

申请人： Yuui Shimizu ,  Tatsuya Kishi

发明人： Yuui Shimizu ,  Tatsuya Kishi

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A magnetic random access memory includes a first interconnection extending to a first direction, a second interconnection extending to a second direction perpendicular to the first direction, a magnetoresistive effect element formed between the first and second interconnections, having one terminal connected to the first interconnection, includes a fixed layer, a recording layer and a nonmagnetic layer, a film thickness of the fixed layer being larger than that of the recording layer, and a width of the fixed layer being larger than that of the recording layer, and configured to reverse a magnetization direction in the recording layer by supplying a first electric current between the fixed layer and the recording layer, and a diode having one terminal connected to the other terminal of the magnetoresistive effect element, and the other terminal connected to the second interconnection, and configured to supply the first electric current in only one direction.

摘要翻译： 磁性随机存取存储器包括延伸到第一方向的第一互连，延伸到垂直于第一方向的第二方向的第二互连，形成在第一和第二互连之间的磁阻效应元件，具有连接到第一互连的一个端子， 包括固定层，记录层和非磁性层，固定层的膜厚度大于记录层的厚度，固定层的宽度大于记录层的厚度， 通过在固定层和记录层之间提供第一电流而形成记录层中的磁化方向，以及二极管，其一端连接到磁阻效应元件的另一端，另一端连接到第二互连， 以仅在一个方向上提供第一电流。

公开(公告)号：US08391040B2

公开(公告)日：2013-03-05

申请号：US13052198

申请日：2011-03-21

申请人： Yoshinao Suzuki ,  Yuui Shimizu

发明人： Yoshinao Suzuki ,  Yuui Shimizu

IPC分类号： G11C5/02

CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C16/06 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first memory chip, a second memory chip, and a control chip. The first chip includes a first inductor configured to transmit/receive a signal, and a memory cell. The second chip is disposed on the first chip and includes a second inductor configured to transmit/receive a signal, and a memory cell. The control chip includes a control circuit configured to control the first and second chips, and a third inductor configured to transmit/receive a signal to/from the first and second inductors. The outer peripheries of the first and second inductors are included in a closed space produced by extending the outer periphery of the third inductor in a direction perpendicular to a plane that includes the third inductor. The inductance of the third inductor is greater than at least one of the inductances of the first and second inductors.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一存储器芯片，第二存储器芯片和控制芯片。 第一芯片包括被配置为发送/接收信号的第一电感器和存储器单元。 第二芯片设置在第一芯片上，并且包括被配置为发送/接收信号的第二电感器和存储单元。 控制芯片包括被配置为控制第一和第二芯片的控制电路和被配置为向/从第一和第二电感器发送/接收信号的第三电感器。 第一和第二电感器的外围包括在通过使第三电感器的外周沿垂直于包括第三电感器的平面的方向延伸而产生的封闭空间。 第三电感器的电感大于第一和第二电感器的电感中的至少一个。

公开(公告)号：US08374032B2

公开(公告)日：2013-02-12

申请号：US13161147

申请日：2011-06-15

申请人： Yuko Namiki ,  Takuya Futatsuyama ,  Yuui Shimizu

发明人： Yuko Namiki ,  Takuya Futatsuyama ,  Yuui Shimizu

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.

摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。

公开(公告)号：US07154775B2

公开(公告)日：2006-12-26

申请号：US10614814

申请日：2003-07-09

申请人： Yuui Shimizu ,  Haruki Toda

发明人： Yuui Shimizu ,  Haruki Toda

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： A magnetic random access memory includes a memory cell array in which memory cells, each having a magnetoresistive element as a storage element, are arranged, word lines respectively connected to rows of the memory cell array, bit lines respectively connected to columns of the memory cell array, row decoders to select the word lines, and a column decoder to select the bit lines. To determine the value of storage data, electrical characteristic values based on storage data stored in the plurality of memory cells are detected, reference data is continuously written in the plurality of memory cells, the reference data written in the plurality of memory cells is continuously read out to detect electrical characteristic values based on the reference data, and the electrical characteristic values based on the storage data are compared with those based on the reference data.

摘要翻译： 磁性随机存取存储器包括一个存储单元阵列，其中排列有各自具有磁阻元件作为存储元件的存储单元，分别连接到存储单元阵列的行的字线，分别连接到存储单元的列的位线 阵列，行解码器选择字线，以及列解码器来选择位线。 为了确定存储数据的值，检测基于存储在多个存储单元中的存储数据的电特性值，将参考数据连续写入多个存储单元，写入多个存储单元的参考数据被连续读取 基于参考数据检测电特性值，并将基于存储数据的电特性值与基于参考数据的电特性值进行比较。

公开(公告)号：US07035137B2

公开(公告)日：2006-04-25

申请号：US10807454

申请日：2004-03-24

申请人： Yoshihisa Iwata ,  Kentaro Nakajima ,  Masayuki Sagoi ,  Yuui Shimizu

发明人： Yoshihisa Iwata ,  Kentaro Nakajima ,  Masayuki Sagoi ,  Yuui Shimizu

IPC分类号： G11C11/00 ,  G11C7/04

CPC分类号： G11C11/15

摘要： A semiconductor memory device comprises word lines, bit lines, memory cells, a row decoder, a column decoder, and a write circuit. The word lines are formed along a first direction. The bit lines are formed along a second direction. Memory cells include magneto-resistive elements and are arranged at intersections of the word lines and the bit lines. The row decoder selects at least one of the word lines. The column decoder selects at least one of the bit lines. The write circuit supplies first and second write currents to a selected word line and selected bit line respectively and writes data into a selected memory cell arranged at the intersection of the selected word line and the selected bit line. The write circuit changes the current values of the first and second write currents according to a temperature change.

摘要翻译： 半导体存储器件包括字线，位线，存储单元，行解码器，列解码器和写电路。 字线沿着第一方向形成。 位线沿着第二方向形成。 存储单元包括磁阻元件，并且布置在字线和位线的交点处。 行解码器选择至少一个字线。 列解码器选择至少一个位线。 写入电路分别向所选择的字线和所选位线提供第一和第二写入电流，并将数据写入布置在所选择的字线和所选位线的交点处的选定存储单元。 写入电路根据温度变化改变第一和第二写入电流的电流值。