公开(公告)号：US20130149572A1

公开(公告)日：2013-06-13

申请号：US13818125

申请日：2012-01-16

申请人： Yuzo Matsuo ,  Ryo Nagai ,  Koichi Kajiyama

发明人： Yuzo Matsuo ,  Ryo Nagai ,  Koichi Kajiyama

IPC分类号： H01M2/34

CPC分类号： H01M2/34 ,  H01M10/482 ,  H01M2200/103

摘要： A battery unit (1) includes battery subunits (11, 12, 13) and a voltage monitoring circuit (30). The battery subunits (11, 12, 13) includes battery modules (110, 120, 130), each having a secondary battery cell (111, 121, 131) and a fuse (112, 122, 132) connected in series. The voltage monitoring circuit (30) monitors the voltage across the terminals of each of the battery subunits (11, 12, 13). Each of the battery subunits (11, 12, 13) includes one battery module or a plurality of battery modules (110, 120, 130) connected in parallel.

摘要翻译： 电池单元（1）包括电池子单元（11,12,13）和电压监视电路（30）。 电池子单元（11,12,13）包括电池模块（110,120,130），每个电池模块具有二次电池单元（111,121,131）和串联连接的保险丝（112,122,132）。 电压监视电路（30）监视每个电池子单元（11,12,13）的端子两端的电压。 每个电池子单元（11,12,13）包括并联连接的一个电池模块或多个电池模块（110,120,130）。

公开(公告)号：US20070031094A1

公开(公告)日：2007-02-08

申请号：US11493917

申请日：2006-07-27

申请人： Misao Watahiki ,  Ryo Nagai ,  Takahiro Sato

发明人： Misao Watahiki ,  Ryo Nagai ,  Takahiro Sato

IPC分类号： G02B6/44

CPC分类号： G02B6/4495

摘要： An optical fiber cable has: a cable portion having an optical fiber tape core wire that a plurality of optical fiber core wires are stacked in parallel, and a cable sheath formed on the plurality of optical fiber core wires; and mold-releasing sheets disposed in parallel with the optical fiber tape core wire. The mold-releasing sheets have an end portion extended from the end of the optical fiber tape core wire. An end of the optical fiber tape core wire is covered by the end portion of the mold-releasing sheet.

摘要翻译： 光纤电缆具有：具有多根光纤芯线并列堆叠的光纤带芯线的电缆部分和形成在多根光纤芯线上的电缆护套; 以及与光纤带芯线并联设置的脱模片。 脱模片具有从光纤带芯线的端部延伸的端部。 光纤带芯线的端部被脱模片的端部覆盖。

公开(公告)号：US07057243B2

公开(公告)日：2006-06-06

申请号：US10648883

申请日：2003-08-27

申请人： Satoru Yamada ,  Ryo Nagai ,  Kiyonori Oyu ,  Ryoichi Nakamura ,  Norikatsu Takaura

发明人： Satoru Yamada ,  Ryo Nagai ,  Kiyonori Oyu ,  Ryoichi Nakamura ,  Norikatsu Takaura

IPC分类号： H01L29/94

CPC分类号： H01L27/10891 ,  H01L21/28061 ,  H01L21/823842 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4941 ,  H01L29/7833

摘要： In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

摘要翻译： 在具有三个或更多个不同费米能级的多晶硅栅电极结构的半导体器件中，具有最低费米能级的P型多晶硅设置在第一N型表面沟道MOS晶体管上。 具有最高费米能级的第一N型多晶硅被布置在第二N型表面沟道MOS晶体管上。 具有最高和最低费米能级之间的中间费米能级并且掺杂有N型杂质和P型杂质的第二N型多晶硅设置在P沟道MOS晶体管上。

公开(公告)号：US20050100773A1

公开(公告)日：2005-05-12

申请号：US10490528

申请日：2003-02-14

申请人： Hiroshi Kashino ,  Yasuo Arishima ,  Shinsuke Shibata ,  Gun Seki ,  Shoji Saibara ,  Ryo Nagai

发明人： Hiroshi Kashino ,  Yasuo Arishima ,  Shinsuke Shibata ,  Gun Seki ,  Shoji Saibara ,  Ryo Nagai

IPC分类号： H01M8/04 ,  H01M8/10 ,  H01M8/24 ,  H01M4/86

CPC分类号： H01M8/1009 ,  H01M8/04186 ,  H01M8/1004 ,  H01M8/2455

摘要： A liquid fuel cell comprising a plurality of unit fuel cells each having a positive electrode (8) for reducing oxygen, a negative electrode (9) for oxidizing liquid fuel, and an electrolyte layer (10) interposed between the positive electrode (8) and the negative electrode (9), and a section (3) for storing liquid fuel (4), wherein power can be generated stably while reducing the size by arranging the plurality of unit fuel cells on the substantially same plane. Each electrolyte layer of the unit fuel cell preferably constitutes a continuous integrated electrolyte layer.

摘要翻译： 一种液体燃料电池，包括多个单元燃料电池，每个单元燃料电池均具有用于还原氧的正电极（8），用于氧化液体燃料的负电极（9）和介于所述正电极（8）和 负极（9）和用于储存液体燃料（4）的部分（3），其中通过将多个单位燃料电池布置在基本相同的平面上，能够稳定地产生功率，同时减小尺寸。 单元燃料电池的每个电解质层优选构成连续的集成电解质层。

公开(公告)号：US06809364B2

公开(公告)日：2004-10-26

申请号：US10630695

申请日：2003-07-31

申请人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

公开(公告)号：US06621110B1

公开(公告)日：2003-09-16

申请号：US09592648

申请日：2000-06-13

申请人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

摘要翻译： 开放位线结构的DRAM具有小于折叠位线结构的DRAM的单元面积，并且易受噪声影响。 开放位线结构的常规DRAM具有大的位线电容，并且易于噪声或具有大的单元面积。 已经没有开放位线结构的DRAM具有小的位线电容，不能被噪声感知并且具有小的单元面积。 本发明形成与位线不对齐的电容器下电极插孔，以减少位线电容。 位线形成为小的宽度，电容器下电极插头从与位线相对应的位置的位置脱位，并且触点形成为减小的直径，以避免增加电池面积。 因此，提供了耐噪声且具有小单元面积的开放位线结构的半导体存储装置。

公开(公告)号：US07687849B2

公开(公告)日：2010-03-30

申请号：US12128796

申请日：2008-05-29

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L29/788

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了一种通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。 在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是 进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US20090233433A1

公开(公告)日：2009-09-17

申请号：US12453737

申请日：2009-05-20

申请人： Satoru Yamada ,  Ryo Nagai

发明人： Satoru Yamada ,  Ryo Nagai

IPC分类号： H01L21/28

CPC分类号： H01L21/28061 ,  H01L21/823842 ,  H01L29/4941

摘要： A method for forming a semiconductor device includes, in order, consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate, implanting boron into the silicon layer, diffusing the boron by heat-treating the silicon layer, implanting phosphorous into the silicon layer, diffusing at least the phosphorous by heat-treating the silicon layer, and patterning the silicon layer by using a dry etching technique.

摘要翻译： 一种形成半导体器件的方法依次包括在半导体衬底上沉积栅极绝缘膜和硅层，将硼注入到硅层中，通过热处理硅层来扩散硼，将磷注入到硅中 层，通过热处理硅层至少扩散至少磷，并通过使用干蚀刻技术图案化硅层。

公开(公告)号：US20060171645A1

公开(公告)日：2006-08-03

申请号：US11322284

申请日：2006-01-03

申请人： Yoshihiro Kodaka ,  Takahiro Sato ,  Ryo Nagai

发明人： Yoshihiro Kodaka ,  Takahiro Sato ,  Ryo Nagai

IPC分类号： G02B6/44

CPC分类号： G02B6/4495 ,  G02B6/4403

摘要： An optical fiber cable in which an optical fiber tape unit can be taken out easily from a sheath is disclosed. An optical fiber cable having a substantially rectangular cross section has one or more optical fiber tape units, a sheath for accommodating the optical fiber tape units, the sheath being of a substantially rectangular cross section, a first pair of notches formed at long sides of the cross section of the sheath, a first line connecting the first pair of notches being across the optical fiber tape units, and second and third pairs of notches formed at the long sides and above and below the first pair of notches, second and third lines connecting the second and third pairs of notches not being across the optical fiber tape units.

摘要翻译： 公开了一种可以从护套容易地取出光纤带单元的光缆。 具有大致矩形横截面的光纤电缆具有一个或多个光纤带单元，用于容纳光纤带单元的护套，护套基本为矩形横截面，第一对凹口形成在 护套的横截面，连接第一对凹口的第一线穿过光纤带单元，以及形成在第一对凹口的长边和上方和下方的第二和第三对切口，第二和第三线连接 第二和第三对缺口不在光纤带单元之间。

公开(公告)号：US06828242B2

公开(公告)日：2004-12-07

申请号：US10223317

申请日：2002-08-20

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L21302

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。 在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是 进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止