公开(公告)号：US5278457A

公开(公告)日：1994-01-11

申请号：US901149

申请日：1992-06-19

申请人： Yuzuru Fujita ,  Seiichi Kawashima ,  Bunichi Fujita ,  Sakoh Ishikawa ,  Noboru Masuda

发明人： Yuzuru Fujita ,  Seiichi Kawashima ,  Bunichi Fujita ,  Sakoh Ishikawa ,  Noboru Masuda

IPC分类号： G06F1/08 ,  G06F1/10 ,  A03K5/15

CPC分类号： G06F1/10 ,  G06F1/08

摘要： The invention relates to method and apparatus for adjusting a clock signal which is supplied to an electronic apparatus. After the turn-on of a power source of the electronic apparatus, it is detected that a temperature of at least a part of devices in the electronic apparatus substantially reaches a saturation state. When the temperature of the device reaches the saturation state, a phase adjustment of the clock signal of the electronic apparatus is executed. After completion of the phase adjustment of the clock signal, its adjusting state is fixed.

摘要翻译： 本发明涉及一种用于调整提供给电子设备的时钟信号的方法和装置。 在电子设备的电源的接通之后，检测到电子设备中的至少一部分设备的温度基本上达到饱和状态。 当器件的温度达到饱和状态时，执行电子设备的时钟信号的相位调整。 在时钟信号的相位调整完成​​后，其调整状态是固定的。

公开(公告)号：US5497263A

公开(公告)日：1996-03-05

申请号：US117525

申请日：1993-09-07

申请人： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

发明人： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

IPC分类号： G06F1/06 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03H11/26 ,  H03K17/296

CPC分类号： H03K5/133 ,  G06F1/10 ,  H03K2005/00071 ,  H03K2005/00097 ,  H03K2005/00195

摘要： A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units. A clock signal supply device for supplying a second clock signal to a logic circuit block, said clock signal supply device having a clock signal generator for generating a first clock signal and a reference signal and a phase adjusting means for adjusting the phase of the first clock signal phased on a phase difference between the first clock signal and the reference signal and outputting the phase-adjusted signal as a second clock signal, wherein the phase adjusting unit comprises a first variable delay circuit capable of delay operation in initial adjustment of the first clock signal, a second variable delay circuit, disposed in series with the first variable delay circuit, for performing the delay operation after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

摘要翻译： 一种可变延迟电路，包括延迟装置，每个延迟装置具有连续连接的多个延迟单元，延迟装置的一些延迟单元连接到信号传输线，其中通过激活或者使多个延迟单元激活来控制延迟时间 根据施加到分别为所述多个延迟单元提供的控制输入端子的控制信号。 一种用于向逻辑电路块提供第二时钟信号的时钟信号提供装置，所述时钟信号提供装置具有用于产生第一时钟信号和参考信号的时钟信号发生器和用于调整第一时钟的相位的相位调整装置 信号相位于第一时钟信号和参考信号之间的相位差，并输出相位调整信号作为第二时钟信号，其中相位调整单元包括能够在第一时钟的初始调整中延迟操作的第一可变延迟电路 信号，与第一可变延迟电路串联布置的第二可变延迟电路，用于在初始调整之后执行延迟操作;以及控制电路，用于控制第一和第二可变延迟电路的延迟时间。

公开(公告)号：US5150068A

公开(公告)日：1992-09-22

申请号：US391782

申请日：1989-08-09

申请人： Seiichi Kawashima ,  Noboru Masuda ,  Shuichi Ishii ,  Bunichi Fujita

发明人： Seiichi Kawashima ,  Noboru Masuda ,  Shuichi Ishii ,  Bunichi Fujita

IPC分类号： G06F1/10 ,  H03K5/13 ,  H03K5/15

CPC分类号： H03K5/13 ,  G06F1/10 ,  H03K5/15066 ,  H03K5/1508

摘要： The present invention provides a clock signal supply method and system. A reference signal and a synchronizing signal are generated, as well as a clock signal, at a clock signal generating source end. Both the reference signal and the synchronizing signal have a period longer than that of the clock signal. The clock signal at a clock signal destination end is frequency divided in synchronism with the synchronizing signal to provide a sample to be compared with the reference signal. The resultant frequency-divided signal is compared with the reference signal in phase. A delay control is made for the clock signal in accordance with the result of the comparison to adjust the phase of the clock signal at the signal destinations.

摘要翻译： 本发明提供了一种时钟信号提供方法和系统。 在时钟信号发生源端产生参考信号和同步信号以及时钟信号。 参考信号和同步信号都具有比时钟信号长的周期。 时钟信号目的地端的时钟信号与同步信号同步地分频，以提供与参考信号进行比较的采样。 将得到的分频信号与参考信号同相进行比较。 根据比较结果对时钟信号进行延迟控制，以调整信号目的地的时钟信号的相位。

公开(公告)号：US5043596A

公开(公告)日：1991-08-27

申请号：US395958

申请日：1989-08-18

申请人： Noboru Masuda ,  Hiroyuki Itoh ,  Bunichi Fujita ,  Seiichi Kawashima ,  Shuichi Ishii

发明人： Noboru Masuda ,  Hiroyuki Itoh ,  Bunichi Fujita ,  Seiichi Kawashima ,  Shuichi Ishii

IPC分类号： G06F1/06 ,  G06F1/10

CPC分类号： G06F1/06 ,  G06F1/10

摘要： The present invention relates to a clock signal supplying device provided with an automatic phase regulating function for preventing errors in the phase regulation due to noise. In the device according to the present invention, there is disposed a reference signal serving as a phase reference, and transmission lines for clock signals and a transmission line for the reference signal are disposed from a clock signal supplying source to devices which are destinations of the distribution of clock signals. The transmission line for the reference signal is adjusted in advance so as to produce no skew. In the device, which is the destination of distribution of the clock signal, there is disposed a variable delay circuit for regulation of the phase of the clock signal and a phase comparing circuit for comparing the output of the variable delay circuit with the phase of the reference signal to output the result of the comparison. In the device according to the present invention, a noise filter is provided which detects phase regulation errors to effect correct phase regulation. Furthermore, the phase regulation is effected while avoiding a period of time wherein noise is apt to be produced.

公开(公告)号：US4847516A

公开(公告)日：1989-07-11

申请号：US123939

申请日：1987-11-23

申请人： Bunichi Fujita ,  Seiichi Kawashima

发明人： Bunichi Fujita ,  Seiichi Kawashima

IPC分类号： H03L7/00 ,  G06F1/10 ,  H03K5/15 ,  H03L7/23

CPC分类号： H03L7/23 ,  G06F1/10

摘要： A system for feeding clock signals to a plurality of load units comprises an oscillator for generating a first clock signal having a predetermined frequency, a plurality of signal lines for transmitting a signal representative of the first clock signal to a plurality of load units, and delays assigned to the plurality of signal lines for adjusting phases of the signal transmitted on a corresponding line at connection points between the oscillator and the load unit. Each load unit is responsive to the signal transmitted on a corresponding signal line for producing second clock signals with a frequency n times greater than that of the second clock signals where n is an integer greater than one. Each load unit further is responsive to the second clock signal for generating a plurality of third clock signals which have discrete phases. The plurality of load units are synchronized with at least one of the plurality of third clock signals.

摘要翻译： 用于将时钟信号馈送到多个负载单元的系统包括用于产生具有预定频率的第一时钟信号的振荡器，用于将表示第一时钟信号的信号发送到多个负载单元的多个信号线，以及延迟 分配给多个信号线，用于调整在振荡器和负载单元之间的连接点处在相应线路上发送的信号的相位。 每个负载单元响应在相应信号线上发送的信号，用于产生频率比第二时钟信号大n倍的频率n倍的频率的第二时钟信号。 每个负载单元进一步响应于第二时钟信号以产生具有离散相位的多个第三时钟信号。 多个负载单元与多个第三时钟信号中的至少一个同步。

公开(公告)号：US4719371A

公开(公告)日：1988-01-12

申请号：US687765

申请日：1984-12-31

申请人： Bunichi Fujita ,  Seiichi Kawashima

发明人： Bunichi Fujita ,  Seiichi Kawashima

IPC分类号： H03K5/04 ,  H03K17/00 ,  H03K17/62 ,  H03K19/086 ,  H03K19/20

CPC分类号： H03K17/005 ,  H03K17/6264 ,  H03K19/086 ,  H03K5/04

摘要： An ordinary differential type gate circuit has two transistors to which complementary inputs are given and which are turned on and off, and complementary type outputs in accordance with the states of the complementary inputs are generated from the collectors of those transistors. In this invention, there are further added a fixed threshold type gate circuit to which is inputted a control signal and a circuit which, when the control signal is inputted to this fixed threshold type gate circuit, generates complementary outputs in constant states irrespective of the states of the complementary inputs in response to the state of the control signal, thereby preventing the inputs applied to the differential type gate circuit from being reflected to the outputs.

摘要翻译： 普通差分型门电路具有两个晶体管，互补输入被给予并且被导通和截止，并且根据这些晶体管的集电极产生互补输入的状态的互补型输出。 在本发明中，进一步添加了一个固定阈值型门电路，输入一个控制信号和一个电路，当控制信号被输入到该固定阈值型门电路时，产生恒定状态的互补输出，不管状态如何 的补偿输入以响应于控制信号的状态，从而防止施加到差分型门电路的输入被反射到输出。

公开(公告)号：US5761253A

公开(公告)日：1998-06-02

申请号：US268410

申请日：1994-06-30

申请人： Yuzuru Fujita ,  Haruhiko Imada ,  Seiichi Kawashima

发明人： Yuzuru Fujita ,  Haruhiko Imada ,  Seiichi Kawashima

IPC分类号： G06F1/10 ,  G06F1/12 ,  G06F13/42 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0682

摘要： A method and an apparatus for enabling a data signal to be transmitted stably at high speed over long distances without using thicker cables and without increasing physical quantities of such resources as transmitting-receiving circuit elements are disclosed. On the transmitting side, the phase of a clock signal relative to the data signal is modified in accordance with the distance between the transmitting and the receiving sides, the clock signal being transmitted along with the data signal. On the receiving side, the incoming data signal is received in synchronism with the received clock signal.

摘要翻译： 一种方法和装置，用于使数据信号能够在不使用较粗的电缆的情况下以高速稳定地传输，而不增加诸如发射 - 接收电路元件的资源的物理量。 在发送侧，相对于数据信号的时钟信号的相位根据发送侧和接收侧之间的距离被修改，时钟信号与数据信号一起发送。 在接收侧，与所接收的时钟信号同步接收输入数据信号。

公开(公告)号：US20090121996A1

公开(公告)日：2009-05-14

申请号：US12270183

申请日：2008-11-13

申请人： Takao TAKANO ,  Seiichi Kawashima

发明人： Takao TAKANO ,  Seiichi Kawashima

IPC分类号： G09G3/36

CPC分类号： G02F1/136227 ,  G02F1/136286

摘要： A liquid crystal display device is provided with: a number of gate signal lines and a number of drain signal lines formed so as to cross the gate signal lines provided on the surface of one of a pair of substrates provided so as to face each other with liquid crystal in between on the liquid crystal side; and thin film transistors connected to a gate signal line and a drain signal line, pixel electrodes to which a video signal is supplied from a drain signal line via a thin film transistor, and a counter electrode to which a reference signal which becomes a reference for the video signal is supplied via a counter voltage signal line provided in pixel regions surrounded by a pair of adjacent gate signal lines and a pair of adjacent drain signal lines, and is characterized in that the above described counter electrodes are formed of a transparent conductive film, the above described pixel electrodes are formed of a transparent conductive film and on the liquid crystal side relative to the above described counter electrodes via an insulating film, and the above described counter voltage signal lines are formed in the direction in which the above described gate signal lines run so as to overlap with the above described gate signal lines via the above described insulating film and be electrically connected to the above described counter electrodes via contact holes created in the above described insulating film.

摘要翻译： 一种液晶显示装置具备：多个栅极信号线和多个漏极信号线，形成为跨越设置在彼此面对的一对基板的表面上的栅极信号线， 在液晶侧之间的液晶; 连接到栅极信号线和漏极信号线的薄膜晶体管，经由薄膜晶体管从漏极信号线向其提供视频信号的像素电极以及作为参考信号的基准信号的对置电极 通过设置在由一对相邻的栅极信号线和一对相邻的漏极信号线围绕的像素区域中的相对电压信号线提供视频信号，其特征在于，上述对置电极由透明导电膜 上述像素电极由透明导电膜形成，并且通过绝缘膜相对于上述相对电极在液晶侧上形成，并且上述对置电压信号线沿着上述栅极 信号线通过上述绝缘膜与上述栅极信号线重叠并且电连接 通过在上述绝缘膜中产生的接触孔将其与上述对置电极连接。

公开(公告)号：US4460817A

公开(公告)日：1984-07-17

申请号：US387665

申请日：1982-06-11

申请人： Mitsukiyo Tani ,  Seiichi Kawashima

发明人： Mitsukiyo Tani ,  Seiichi Kawashima

IPC分类号： H05K3/34 ,  B23K1/00 ,  B23K3/00 ,  B23K3/04 ,  B23K1/12

CPC分类号： B23K3/00 ,  B23K1/0004

摘要： A small-sized light-weight resistance reflow soldering apparatus for modifying the wiring pattern on a printed circuit board, with the soldering apparatus including a heating device with an adjustable weight, a supporting mechanism for a vertically movably supporting the heating device, a welding power supply for making the heating device produce heat enough to melt the solder for a predetermined time length, and a case accomodating these constituents. The soldering is effected by the heating device which produces the heat while being pressed against the jointing surface.

摘要翻译： 一种用于修改印刷电路板上的布线图案的小型轻量电阻回流焊接装置，该焊接装置包括具有可调节重量的加热装置，用于垂直运动地支撑加热装置的支撑机构，焊接功率 用于使加热装置产生足够的热量以使焊料熔化预定时间长度的供应，以及适应这些成分的壳体。 焊接由加热装置实现，该加热装置在被压靠在接合表面上时产生热量。

公开(公告)号：US08773341B2

公开(公告)日：2014-07-08

申请号：US12270183

申请日：2008-11-13

申请人： Takao Takano ,  Seiichi Kawashima

发明人： Takao Takano ,  Seiichi Kawashima

IPC分类号： G09G3/36

CPC分类号： G02F1/136227 ,  G02F1/136286

摘要： A liquid crystal display device including a liquid crystal panel including liquid crystal sealed between a pair of substrates; a plurality of gate signal lines and a plurality of drain signal lines formed to cross each other on one of said pair of substrates; a pixel region surrounded by a pair of adjacent gate signal lines and a pair of adjacent drain signal lines; a thin film transistor provided in the pixel region and connected to at least one of the pair of adjacent gate signal lines and at least one of the pair of drain signal lines; a pixel electrode provided in the pixel region and supplied with a video signal via the thin film transistor; and a counter electrode provided in the pixel region and supplied with a reference signal via a counter voltage signal line, the reference signal being a reference for the video signal.

摘要翻译： 一种液晶显示装置，包括：液晶面板，其包含密封在一对基板之间的液晶; 多个栅极信号线和多条漏极信号线，形成为在所述一对基板之一上彼此交叉; 由一对相邻的栅极信号线和一对相邻的漏极信号线包围的像素区域; 设置在所述像素区域中并连接到所述一对相邻栅极信号线中的至少一个和所述一对漏极信号线中的至少一个的薄膜晶体管; 像素电极，设置在像素区域中并通过薄膜晶体管提供视频信号; 以及设置在所述像素区域中并经由对电压信号线提供参考信号的对电极，所述参考信号是所述视频信号的基准。