公开(公告)号：US11995389B2

公开(公告)日：2024-05-28

申请号：US17417877

申请日：2019-10-14

Applicant: ZTE Corporation

Inventor： Xinjian Chen ,  Yonghui Ren ,  Rongxing Ban ,  Yingxin Wang

IPC: G06F30/39 ,  G06F13/40 ,  G06F30/394 ,  G06F115/12

CPC classification number: G06F30/394 ,  G06F13/4068 ,  G06F2115/12

Abstract: Provided are a connector structure, and a skew calculation method and device. Specifically, the connector structure includes: a first Printed Circuit Board (PCB) (12), which includes a first board (122) and a second board (124), and is connected to a testing device; and a second PCB (14), which includes a third board (142) and a fourth board (144), and is connected to the testing device. The first board (122) is connected to the third board (142) through a connector (16).

公开(公告)号：US10064271B2

公开(公告)日：2018-08-28

申请号：US15108405

申请日：2014-05-21

Applicant: ZTE CORPORATION

Inventor： Bi Yi ,  Fengchao Ma ,  Yonghui Ren ,  Wang Xiong ,  Yingxin Wang

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/10303 ,  H05K2203/0207 ,  H05K2203/16

Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.

公开(公告)号：US20230284375A1

公开(公告)日：2023-09-07

申请号：US18315589

申请日：2023-05-11

Applicant: ZTE Corporation

Inventor： Changgang YIN ,  Zhongmin Wei ,  Bi Yi ,  Yonghui Ren

IPC: H05K1/02

CPC classification number: H05K1/0251 ,  H05K1/0245

Abstract: The present application relates to a circuit technology, and discloses a printed circuit board, including: a board body portion comprising a plurality of core boards and a plurality of dielectric layers, the plurality of core boards including a plurality of conductor layers, and the plurality of conductor layers including a differential signal transmission layer located on a surface layer of the board body portion and a differential signal line out layer located on an inner layer of the board body portion; two opposite differential signal holes located on the board body portion, the two differential signal holes being passed sequentially from the differential signal transmission layer to the differential signal line out layer through at least a portion of the core boards and connect the differential signal transmission layer to the differential signal line out layer; and two slotted conductive posts located between the two differential signal holes.