公开(公告)号：US10064271B2

公开(公告)日：2018-08-28

申请号：US15108405

申请日：2014-05-21

Applicant: ZTE CORPORATION

Inventor： Bi Yi ,  Fengchao Ma ,  Yonghui Ren ,  Wang Xiong ,  Yingxin Wang

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/10303 ,  H05K2203/0207 ,  H05K2203/16

Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.

公开(公告)号：US20230284375A1

公开(公告)日：2023-09-07

申请号：US18315589

申请日：2023-05-11

Applicant: ZTE Corporation

Inventor： Changgang YIN ,  Zhongmin Wei ,  Bi Yi ,  Yonghui Ren

IPC: H05K1/02

CPC classification number: H05K1/0251 ,  H05K1/0245

Abstract: The present application relates to a circuit technology, and discloses a printed circuit board, including: a board body portion comprising a plurality of core boards and a plurality of dielectric layers, the plurality of core boards including a plurality of conductor layers, and the plurality of conductor layers including a differential signal transmission layer located on a surface layer of the board body portion and a differential signal line out layer located on an inner layer of the board body portion; two opposite differential signal holes located on the board body portion, the two differential signal holes being passed sequentially from the differential signal transmission layer to the differential signal line out layer through at least a portion of the core boards and connect the differential signal transmission layer to the differential signal line out layer; and two slotted conductive posts located between the two differential signal holes.

公开(公告)号：US11696399B2

公开(公告)日：2023-07-04

申请号：US17635916

申请日：2020-09-15

Applicant: ZTE Corporation

Inventor： Changgang Yin ,  Bi Yi ,  Zhongmin Wei

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H05K1/115 ,  H05K2201/0939 ,  H05K2201/09481 ,  H05K2201/09854

Abstract: A circuit board is disclosed, including a circuit board body and at least one via apparatus provided on the circuit board body. The via apparatus includes a via (101) formed on the circuit board body, a via pad (201) surrounding the via and separately provided from the via, and an electrical conductor (301) electrically connecting the via pad (201) with the via (101).

公开(公告)号：US11457529B2

公开(公告)日：2022-09-27

申请号：US17282410

申请日：2019-09-27

Applicant: ZTE CORPORATION

Inventor： Changgang Yin ,  Yingxin Wang ,  Bi Yi ,  Huazhang Cao

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/10 ,  H05K3/36 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H01L21/768 ,  H01L23/48 ,  H01L23/66 ,  H05K3/00

Abstract: Provided are a circuit board, an apparatus and a method for forming a via hole structure. A via hole structure formed on a main body (10) of a circuit board includes a hole (12) enclosed by a conductive layer in the main body (10), the conductive layer constitutes a wall (11) of the hole (12), and a dielectric filling layer (13), which has a dielectric constant smaller than that of the main body (10), is disposed between at least a portion of the wall (11) of the hole (12) and the main body (10), so that the parasitic capacitance of a via hole is decreased, and the impedance of the via hole is increased to become closer to the impedance of a transmission line, thereby effectively improving impedance continuity of a system link.