公开(公告)号：US11457529B2

公开(公告)日：2022-09-27

申请号：US17282410

申请日：2019-09-27

Applicant: ZTE CORPORATION

Inventor： Changgang Yin ,  Yingxin Wang ,  Bi Yi ,  Huazhang Cao

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/10 ,  H05K3/36 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H01L21/768 ,  H01L23/48 ,  H01L23/66 ,  H05K3/00

Abstract: Provided are a circuit board, an apparatus and a method for forming a via hole structure. A via hole structure formed on a main body (10) of a circuit board includes a hole (12) enclosed by a conductive layer in the main body (10), the conductive layer constitutes a wall (11) of the hole (12), and a dielectric filling layer (13), which has a dielectric constant smaller than that of the main body (10), is disposed between at least a portion of the wall (11) of the hole (12) and the main body (10), so that the parasitic capacitance of a via hole is decreased, and the impedance of the via hole is increased to become closer to the impedance of a transmission line, thereby effectively improving impedance continuity of a system link.

公开(公告)号：US11995389B2

公开(公告)日：2024-05-28

申请号：US17417877

申请日：2019-10-14

Applicant: ZTE Corporation

Inventor： Xinjian Chen ,  Yonghui Ren ,  Rongxing Ban ,  Yingxin Wang

IPC: G06F30/39 ,  G06F13/40 ,  G06F30/394 ,  G06F115/12

CPC classification number: G06F30/394 ,  G06F13/4068 ,  G06F2115/12

Abstract: Provided are a connector structure, and a skew calculation method and device. Specifically, the connector structure includes: a first Printed Circuit Board (PCB) (12), which includes a first board (122) and a second board (124), and is connected to a testing device; and a second PCB (14), which includes a third board (142) and a fourth board (144), and is connected to the testing device. The first board (122) is connected to the third board (142) through a connector (16).

公开(公告)号：US10064271B2

公开(公告)日：2018-08-28

申请号：US15108405

申请日：2014-05-21

Applicant: ZTE CORPORATION

Inventor： Bi Yi ,  Fengchao Ma ,  Yonghui Ren ,  Wang Xiong ,  Yingxin Wang

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/10303 ,  H05K2203/0207 ,  H05K2203/16

Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.