公开(公告)号：US20060252226A1

公开(公告)日：2006-11-09

申请号：US11485599

申请日：2006-07-12

申请人： Zarchary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Zarchary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/76

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/1087 ,  H01L27/1203

摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

公开(公告)号：US20050287718A1

公开(公告)日：2005-12-29

申请号：US10710256

申请日：2004-06-29

申请人： Zachary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Zachary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/00 ,  H01L21/334 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/1087 ,  H01L27/1203

摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

摘要翻译： 本发明提供了一种在本体硅区域中的指状去耦电容器，其通过在本体硅区域中蚀刻一系列最小或次最小沟槽而形成，氧化这些沟槽，从至少一个或多个不相交的沟槽中去除氧化物， 具有原位掺杂多晶硅的沟槽，后来通过离子注入掺杂的本征多晶硅，或者用金属柱（例如钨）填充并形成标准互连到电容器板。

公开(公告)号：US20050151213A1

公开(公告)日：2005-07-14

申请号：US10707746

申请日：2004-01-08

申请人： Jon Casey ,  William Ferrante ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Jon Casey ,  William Ferrante ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/28 ,  G01K7/22 ,  H01C7/00 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L21/00 ,  H01L27/14 ,  H01L29/82 ,  H01L31/058

CPC分类号： H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

摘要： A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).

摘要翻译： 提供了用于形成热敏电阻的结构和方法。 隔离结构形成在至少包括单晶半导体的上层的基板中。 一层自杀化合物前体沉积在隔离区和上层上。 然后将自对准硅化物前体与上层反应以形成与上层自对准的自对准硅化物。 最后，除去自对准硅胶前体的未反应部分，同时在作为热敏电阻体的隔离区域上保留一部分自杀化合物前体。 一种替代的集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料的区域形成。

公开(公告)号：US20050275054A1

公开(公告)日：2005-12-15

申请号：US10853800

申请日：2004-05-25

申请人： Zachary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Zachary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： G01K7/01 ,  H01L27/02 ,  H01L29/66 ,  H01L31/0392

CPC分类号： H01L27/0248 ,  G01K7/01 ,  H01L29/66992

摘要： A thermal monitor diode is provided that comprises a silicon thin film on an insulator mounted on a silicon substrate. An opening extends through the silicon thin film and through the insulator and partially into the silicon substrate and terminates at an end wall. A conductive material is disposed in the opening and extends to the end wall. The substrate has a P/N junction formed therein adjacent the end wall, and an insulating spacer material surrounds the conductive material and is sufficiently thin to allow temperature excursions in the silicon thin film to pass therethrough. The invention also contemplates a method of forming the diode.

摘要翻译： 提供一种热监测二极管，其包括安装在硅衬底上的绝缘体上的硅薄膜。 开口延伸穿过硅薄膜并穿过绝缘体并部分地延伸到硅衬底中并终止于端壁。 导电材料设置在开口中并延伸到端壁。 衬底具有邻近端壁形成的P / N结，并且绝缘间隔物材料围绕导电材料并且足够薄以允许硅薄膜中的温度偏移通过。 本发明还考虑了形成二极管的方法。

公开(公告)号：US20070145373A1

公开(公告)日：2007-06-28

申请号：US11684306

申请日：2007-03-09

申请人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

发明人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

IPC分类号： H01L31/00 ,  C30B21/04 ,  H01L29/04 ,  H01L29/00

CPC分类号： H01L29/045 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.

摘要翻译： 本发明提供一种用于制造包括底部半导体层的混合衬底的外延压印工艺; 存在于所述底部半导体层顶部的连续掩埋绝缘层; 以及存在于所述连续掩埋绝缘层上的顶部半导体层，其中所述顶部半导体层包括具有不同晶体取向的分离的平面半导体区域，所述分开的平面半导体区域彼此隔离。 利用外延生长，晶片接合和再结晶退火的本发明的外延印刷方法。

公开(公告)号：US20070190740A1

公开(公告)日：2007-08-16

申请号：US11733249

申请日：2007-04-10

申请人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

发明人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

IPC分类号： H01L21/76

CPC分类号： H01L29/78687 ,  H01L21/26533 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78603

摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.

摘要翻译： 提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。 增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。 在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

公开(公告)号：US20050186744A1

公开(公告)日：2005-08-25

申请号：US10785895

申请日：2004-02-24

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier, ,  Carl Radens ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier, ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/425 ,  H01L21/8234 ,  H01L29/423

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/6659

摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.

摘要翻译： 反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响 旨在改变装置的串联电阻。 逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列 为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻 去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

公开(公告)号：US07772649B2

公开(公告)日：2010-08-10

申请号：US12036325

申请日：2008-02-25

申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.

摘要翻译： 将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。 将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。 去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。 在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。 形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

公开(公告)号：US20090212362A1

公开(公告)日：2009-08-27

申请号：US12036325

申请日：2008-02-25

申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/84 ,  H01L29/786

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.

摘要翻译： 将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。 将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。 去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。 在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。 形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

公开(公告)号：US20070182030A1

公开(公告)日：2007-08-09

申请号：US11347413

申请日：2006-02-03

申请人： William Ma ,  Jack Mandelman ,  Carl Radens ,  William Tonti

发明人： William Ma ,  Jack Mandelman ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/66772 ,  H01L29/78612 ,  H01L29/78624 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了制造高压晶体管的第一种方法。 第一种方法包括以下步骤：（1）提供包括在绝缘体上硅（SOI）层之下的绝缘体层下面的体硅层的衬底; 以及（2）形成包括SOI层中的晶体管的扩散区域的晶体管节点的一个或多个部分。 晶体管节点的一部分适于将晶体管内的大于约5V的电压减小到小于约3V的电压。提供了许多其它方面。