公开(公告)号：US20130264609A1

公开(公告)日：2013-10-10

申请号：US13636127

申请日：2012-05-16

申请人： Zengfeng Di ,  Jiantao Bian ,  Miao Zhang ,  Xi Wang

发明人： Zengfeng Di ,  Jiantao Bian ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L29/66 ,  H01L29/778

CPC分类号： H01L29/66431 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/28264 ,  H01L21/8258 ,  H01L21/84 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78

摘要： The present invention provides a semiconductor structure with a hybrid of Ge and a group III-V material coplanar and a preparation method thereof. A heterogeneously integrated semiconductor structure with Ge and a group III-V semiconductor material coplanar includes at least one Ge substrate formed on a bulk silicon substrate, and the other substrate is the group III-V semiconductor material formed on the Ge semiconductor. The preparation method includes: preparing a Ge semiconductor layer on a bulk silicon substrate; preparing a group III-V semiconductor material layer on the Ge semiconductor layer; performing first photolithography and etching to make a patterned window to a Ge layer so as to form a recess; preparing a spacer in the recess; preparing a Ge film through selective epitaxial growth; performing chemical mechanical polishing to obtain a heterogeneously integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar; removing the spacer and a defect part of the Ge layer close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high performance CMOS device including a Ge channel PMOS and a group III-V channel NMOS by forming an MOS structure.

摘要翻译： 本发明提供了具有Ge和III-V族III族材料共面的混合物的半导体结构及其制备方法。 具有Ge和III-V族半导体材料共面的非均匀集成半导体结构包括形成在体硅衬底上的至少一个Ge衬底，而另一衬底是形成在Ge半导体上的III-V族半导体材料。 制备方法包括：在体硅衬底上制备Ge半导体层; 在Ge半导体层上制备III-V族III族半导体材料层; 进行第一光刻和蚀刻，以将图案化的窗口制成Ge层以形成凹部; 在凹槽中制备间隔物; 通过选择性外延生长制备Ge膜; 进行化学机械抛光以获得具有Ge和III-V族半导体材料共面的杂化物的非均匀集成的半导体结构; 去除间隔物和接近间隔物的Ge层的缺陷部分; 实现Ge与III-V族III族半导体材料之间的隔离; 以及通过形成MOS结构来制备包括Ge沟道PMOS和III-V族沟道NMOS的高性能CMOS器件。

公开(公告)号：US20130062696A1

公开(公告)日：2013-03-14

申请号：US13636128

申请日：2012-05-16

申请人： Zengfeng Di ,  Jiantao Bian ,  Miao Zhang ,  Xi Wang

发明人： Zengfeng Di ,  Jiantao Bian ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L27/12 ,  H01L21/20 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/8258

摘要： The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor. The preparation method for forming the semiconductor structure includes: preparing a global Ge on insulator substrate structure; preparing a group III-V semiconductor material layer on the Ge on insulator substrate structure; performing photolithography and etching for the first time to make a patterned window to the above of a Ge layer to form a recess; preparing a spacer in the recess; preparing a Ge film by selective epitaxial growth; performing a chemical mechanical polishing to obtain the heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material being coplanar; removing the spacer and a defective Ge layer part close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high-performance CMOS device including a Ge PMOS and a III-V NMOS by forming an MOS structure.

摘要翻译： 本发明提供具有共面锗（Ge）和III-V的杂化物的SOI半导体结构及其制备方法。 具有Ge和在绝缘体上共面的III-V族半导体材料的混合物的异质集成半导体结构包括形成在绝缘层上的至少一个Ge衬底，而另一衬底是形成在Ge上的III-V族半导体材料 半导体。 用于形成半导体结构的制备方法包括：制备全局Ge绝缘体衬底结构; 在Ge绝缘体衬底结构上制备III-V族III族半导体材料层; 第一次进行光刻和蚀刻，以形成图案化窗口到Ge层的上方以形成凹部; 在凹槽中制备间隔物; 通过选择性外延生长制备Ge膜; 进行化学机械抛光以获得具有Ge和III-V族半导体材料共面的混合物的异质集成半导体结构; 去除间隔物和靠近隔离物的缺陷Ge层部分; 实现Ge与III-V族III族半导体材料之间的隔离; 以及通过形成MOS结构来制备包括Ge PMOS和III-V NMOS的高性能CMOS器件。

公开(公告)号：US08501593B2

公开(公告)日：2013-08-06

申请号：US13260757

申请日：2011-07-25

申请人： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

发明人： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

IPC分类号： H01L27/092

CPC分类号： C30B29/52 ,  C30B1/00 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/456

摘要： The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance.

摘要翻译： 本发明公开了一种通过引入Al中间层的NiSiGe外延生长方法，包括在SiGe层的表面上沉积Al薄膜，随后在Al薄膜上沉积Ni层，然后在Ni之间进行退火处理 SiGe层的SiGe材料，形成NiSiGe材料。 由于Al中间层的阻挡效应，NiSiGe层具有单晶结构，与SiGe衬底的平坦界面，厚度可达0.3nm，显着提高了界面性能。

公开(公告)号：US08350298B2

公开(公告)日：2013-01-08

申请号：US12810619

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L27/12 ,  H01L21/00 ,  H01L21/84 ,  H01L27/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L29/42392 ,  H01L29/78696

摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects.

摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下，器件具有混合材料，GAA结构，具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，防止多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US20110248354A1

公开(公告)日：2011-10-13

申请号：US12810619

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L27/092

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L29/42392 ,  H01L29/78696

摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects.

摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下，器件具有混合材料，GAA结构，具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，防止多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US08264042B2

公开(公告)日：2012-09-11

申请号：US12810574

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

IPC分类号： H01L27/12

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/42392

摘要： A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

摘要翻译： 混合取向累积模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由p型Si（110）和n型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 根据本发明的装置结构相当简单，紧凑且高度集成。 在积累模式中，电流流过整个跑道状通道。 所公开的装置导致高载流子迁移率。 同时防止多晶硅栅极耗尽和短沟道效应，并且阈值电压增加。

公开(公告)号：US20110254100A1

公开(公告)日：2011-10-20

申请号：US12810648

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L27/092

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/78696

摘要： A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented.

摘要翻译： Ge和Si混合材料堆积模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由p型Ge和n型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在积累模式中，电流流过整个跑道状通道。 所公开的器件具有高的载流子迁移率，高的器件驱动电流，并且保持器件的电气完整性。 同时，防止了多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US08330229B2

公开(公告)日：2012-12-11

申请号：US12810740

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L27/092

CPC分类号： H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/78696

摘要： A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects.

摘要翻译： 混合取向反转模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由n型Si（110）和p型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 根据本发明的装置结构相当简单，紧凑且高度集成。 在反转模式中，器件具有不同的取向通道，GAA结构具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，并防止多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US20120112283A1

公开(公告)日：2012-05-10

申请号：US13002303

申请日：2010-12-16

申请人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

发明人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L27/12 ,  H01L21/283

CPC分类号： H01L21/84 ,  H01L27/0255 ,  H01L27/1203

摘要： The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.

摘要翻译： 本发明公开了一种SOI CMOS电路中的ESD保护结构。 ESD保护结构包括各种纵向（垂直）PN结结构，其具有用于电流的显着扩大的接合面积。 所得到的装置实现了增加的大电流释放能力。 还公开了制造ESD保护纵向PN结的品种的工艺。 所公开的制造工艺与当前SOI技术的兼容性降低了实施成本并提高了集成度。

公开(公告)号：US20110254013A1

公开(公告)日：2011-10-20

申请号：US12810574

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

IPC分类号： H01L27/092

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/42392

摘要： A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

摘要翻译： 混合取向累积模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由p型Si（110）和n型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 根据本发明的装置结构相当简单，紧凑且高度集成。 在积累模式中，电流流过整个跑道状通道。 所公开的装置导致高载流子迁移率。 同时防止多晶硅栅极耗尽和短沟道效应，并且阈值电压增加。