公开(公告)号：US20090014710A1

公开(公告)日：2009-01-15

申请号：US12281034

申请日：2007-03-06

申请人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

发明人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

摘要翻译： 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

公开(公告)号：US08013711B2

公开(公告)日：2011-09-06

申请号：US12280013

申请日：2007-02-27

申请人： Zhiqiang Wei ,  Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima

发明人： Zhiqiang Wei ,  Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima

IPC分类号： H01C7/10

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683 ,  Y10T29/49099

摘要： A method for manufacturing a variable resistance element includes the steps of: depositing a variable resistance material (106) in a contact hole (105), which is formed on an interlayer insulating layer (104) on a substrate and has a lower electrode (103) at a bottom portion thereof, such that an upper surface of the variable resistance material (106) in the contact hole (105) is located lower than an upper surface of the interlayer insulating layer (104); depositing an upper electrode material on the deposited variable resistance material (106) such that an upper surface of the upper electrode material in the contact hole (105) is located higher than the upper surface of the interlayer insulating layer (104); and element-isolating by a CMP the variable resistance element including the variable resistance material (106) and the upper electrode material.

摘要翻译： 一种制造可变电阻元件的方法包括以下步骤：将可变电阻材料（106）沉积在形成在衬底上的层间绝缘层（104）上的接触孔（105）中，并具有下电极（103） ），使得所述接触孔（105）中的所述可变电阻材料（106）的上表面位于所述层间绝缘层（104）的上表面以下。 在所述沉积的可变电阻材料（106）上沉积上电极材料，使得所述接触孔（105）中的上电极材料的上表面位于比所述层间绝缘层（104）的上表面高; 以及通过CMP对包括可变电阻材料（106）和上电极材料的可变电阻元件进行元件隔离。

公开(公告)号：US07919774B2

公开(公告)日：2011-04-05

申请号：US12709148

申请日：2010-02-19

申请人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

发明人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

IPC分类号： H01L29/68 ,  H01L21/34

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

摘要翻译： 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

公开(公告)号：US20100225438A1

公开(公告)日：2010-09-09

申请号：US12280013

申请日：2007-02-27

申请人： Zhiqiang Wei ,  Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima

发明人： Zhiqiang Wei ,  Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima

IPC分类号： H01C7/10 ,  H01C17/06

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683 ,  Y10T29/49099

摘要： A method for manufacturing a variable resistance element includes the steps of: depositing a variable resistance material (106) in a contact hole (105), which is formed on an interlayer insulating layer (104) on a substrate and has a lower electrode (103) at a bottom portion thereof, such that an upper surface of the variable resistance material (106) in the contact hole (105) is located lower than an upper surface of the interlayer insulating layer (104); depositing an upper electrode material on the deposited variable resistance material (106) such that an upper surface of the upper electrode material in the contact hole (105) is located higher than the upper surface of the interlayer insulating layer (104); and element-isolating by a CMP the variable resistance element including the variable resistance material (106) and the upper electrode material.

摘要翻译： 一种制造可变电阻元件的方法包括以下步骤：将可变电阻材料（106）沉积在形成在衬底上的层间绝缘层（104）上的接触孔（105）中，并具有下电极（103） ），使得所述接触孔（105）中的所述可变电阻材料（106）的上表面位于所述层间绝缘层（104）的上表面以下。 在所述沉积的可变电阻材料（106）上沉积上电极材料，使得所述接触孔（105）中的上电极材料的上表面位于比所述层间绝缘层（104）的上表面高; 以及通过CMP对包括可变电阻材料（106）和上电极材料的可变电阻元件进行元件隔离。

公开(公告)号：US07692178B2

公开(公告)日：2010-04-06

申请号：US12281034

申请日：2007-03-06

申请人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

发明人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

摘要翻译： 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

公开(公告)号：US20100061142A1

公开(公告)日：2010-03-11

申请号：US12532552

申请日：2007-11-30

申请人： Koji Arita ,  Takeshi Takagi ,  Takumi Mikawa ,  Yoshio Kawashima ,  Zhiqiang Wei

发明人： Koji Arita ,  Takeshi Takagi ,  Takumi Mikawa ,  Yoshio Kawashima ,  Zhiqiang Wei

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： Memory elements (3) arranged in matrix in a memory apparatus (21), each includes a resistance variable element (1) which changes an electrical resistance value in response to an applied electrical pulse having a positive polarity or a negative polarity and maintains the changed electrical resistance value, and a current suppressing element (2) for suppressing a current flowing when the electrical pulse is applied to the resistance variable element. The current suppressing element includes a first electrode, a second electrode, and a current suppressing layer provided between the first electrode and the second electrode, and the current suppressing layer comprises SiNx (x: positive actual number).

摘要翻译： 在存储装置（21）中排列成矩阵的存储元件（3），每个包括电阻变化元件（1），其响应于所施加的具有正极性或负极性的电脉冲改变电阻值，并保持改变 电阻值和电流抑制元件（2），用于抑制当电脉冲施加到电阻可变元件时流动的电流。 电流抑制元件包括第一电极，第二电极和设置在第一电极和第二电极之间的电流抑制层，并且电流抑制层包括SiNx（x：正实数）。

公开(公告)号：US20100200852A1

公开(公告)日：2010-08-12

申请号：US12709148

申请日：2010-02-19

申请人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

发明人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

IPC分类号： H01L29/68 ,  H01L21/34

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

摘要翻译： 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

公开(公告)号：US08471235B2

公开(公告)日：2013-06-25

申请号：US13132822

申请日：2009-12-04

申请人： Yoshio Kawashima ,  Takumi Mikawa ,  Zhiqiang Wei ,  Atsushi Himeno

发明人： Yoshio Kawashima ,  Takumi Mikawa ,  Zhiqiang Wei ,  Atsushi Himeno

IPC分类号： H01L29/02

CPC分类号： H01L27/0688 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608

摘要： A nonvolatile memory element includes a substrate; a lower electrode layer and a resistive layer sequentially formed on the substrate; a resistance variable layer formed on the resistive layer; a wire layer formed above the lower electrode layer; an interlayer insulating layer disposed between the substrate and the wire layer and covering at least the lower electrode layer and the resistive layer, the interlayer insulating layer being provided with a contact hole extending from the wire layer to the resistance variable layer; and an upper electrode layer formed inside the contact hole such that the upper electrode layer is connected to the resistance variable layer and to the wire layer; resistance values of the resistance variable layer changing reversibly in response to electric pulses applied between the lower electrode layer and the upper electrode layer.

摘要翻译： 非易失性存储元件包括：基板; 在基板上依次形成下电极层和电阻层; 形成在电阻层上的电阻变化层; 形成在所述下电极层的上方的导线层; 层间绝缘层，设置在所述基板和所述线层之间，并且至少覆盖所述下电极层和所述电阻层，所述层间绝缘层设置有从所述导线层延伸到所述电阻变化层的接触孔; 以及形成在所述接触孔内部的上电极层，使得所述上电极层连接到所述电阻变化层和所述导线层; 电阻变化层的电阻值响应于施加在下电极层和上电极层之间的电脉冲而可逆地改变。

公开(公告)号：US20110233511A1

公开(公告)日：2011-09-29

申请号：US13132822

申请日：2009-12-04

申请人： Yoshio Kawashima ,  Takumi Mikawa ,  Zhiqiang Wei ,  Atsushi Himeno

发明人： Yoshio Kawashima ,  Takumi Mikawa ,  Zhiqiang Wei ,  Atsushi Himeno

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L27/0688 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608

摘要： A nonvolatile memory element (10) of the present invention comprises a substrate (11); a lower electrode layer (15) and a resistive layer (16) sequentially formed on the substrate (11); a resistance variable layer (31) formed on the resistive layer (16); a wire layer (20) formed above the lower electrode layer (15); an interlayer insulating layer (17) disposed between the substrate (11) and the wire layer (20) and covering at least the lower electrode layer (15) and the resistive layer (16), the interlayer insulating layer being provided with a contact hole (26) extending from the wire layer (20) to the resistance variable layer (31); and an upper electrode layer (19) formed inside the contact hole (26) such that the upper electrode layer is connected to the resistance variable layer (31) and to the wire layer (20); resistance values of the resistance variable layer (31) changing reversibly in response to electric pulses applied between the lower electrode layer (15) and the upper electrode layer (19).

摘要翻译： 本发明的非易失性存储元件（10）包括衬底（11）; 依次形成在所述基板（11）上的下电极层（15）和电阻层（16）。 形成在电阻层（16）上的电阻变化层（31）; 在所述下电极层（15）的上方形成的导线层（20）。 设置在所述基板（11）和所述导线层（20）之间并且至少覆盖所述下电极层（15）和所述电阻层（16）的层间绝缘层（17），所述层间绝缘层设置有接触孔 （26）从所述导线层（20）延伸到所述电阻变化层（31）; 以及形成在所述接触孔（26）内部的上电极层（19），使得所述上电极层连接到所述电阻变化层（31）和所述导线层（20）; 电阻变化层（31）的电阻值响应于施加在下电极层（15）和上电极层（19）之间的电脉冲而可逆地变化。

公开(公告)号：US07981760B2

公开(公告)日：2011-07-19

申请号：US12669812

申请日：2009-05-07

申请人： Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

发明人： Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

IPC分类号： H01L21/00

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

摘要： A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.

摘要翻译： 一种用于制造使上部电极和下部电极之间的形状偏移最小化的非易失性存储元件的方法，包括：依次沉积导电的连接电极层，下部电极层和可变电阻层 的非贵金属氮化物，并且是导电的，由贵金属制成的上电极层和掩模层; 将掩模层形成为预定形状; 通过使用掩模层作为掩模通过蚀刻将上电极层，可变电阻层和下电极层形成为预定形状; 并且同时去除已经通过蚀刻暴露的掩模和连接电极层的区域。