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248 条记录 (耗时 0.025 秒)

    Input/output driver swing control and supply noise rejection
    1.
    发明授权
    Input/output driver swing control and supply noise rejection 有权
    输入/输出驱动器摆幅控制和电源噪声抑制

    公开(公告)号：US08143911B2

    公开(公告)日：2012-03-27

    申请号：US12060251

    申请日：2008-03-31

    申请人： Zuoguo Wu ,  Feng Chen ,  Sanjay Dabral

    发明人： Zuoguo Wu ,  Feng Chen ,  Sanjay Dabral

    IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/0175

    CPC分类号： H04L25/0276

    摘要： In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a reference voltage and generate a difference therebetween. An integrator is to integrate the difference between the average transmitter output voltage and the reference voltage over time. The integrated difference is fed back to the transmitter to bias the transmitter.

    摘要翻译： 通常，在一个方面，本公开描述了一种具有平均器以接收发射机的差分输出电压并产生平均发射机输出电压的装置。 比较器将平均发射机输出电压与参考电压进行比较，并产生它们之间的差值。 积分器将整合平均发射机输出电压和参考电压随时间的差异。 积分差值被反馈给发射机以偏置发射机。

    INPUT/OUTPUT DRIVER SWING CONTROL AND SUPPLY NOISE REJECTION
    2.
    发明申请
    INPUT/OUTPUT DRIVER SWING CONTROL AND SUPPLY NOISE REJECTION 有权
    输入/输出驱动器控制和供电噪声抑制

    公开(公告)号：US20090245416A1

    公开(公告)日：2009-10-01

    申请号：US12060251

    申请日：2008-03-31

    申请人： Zuoguo Wu ,  Feng Chen ,  Sanjay Dabral

    发明人： Zuoguo Wu ,  Feng Chen ,  Sanjay Dabral

    IPC分类号： H04L25/49

    CPC分类号： H04L25/0276

    摘要： In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a reference voltage and generate a difference therebetween. An integrator is to integrate the difference between the average transmitter output voltage and the reference voltage over time. The integrated difference is fed back to the transmitter to bias the transmitter.

    摘要翻译： 通常，在一个方面，本公开描述了一种具有平均器以接收发射机的差分输出电压并产生平均发射机输出电压的装置。 比较器将平均发射机输出电压与参考电压进行比较，并产生它们之间的差值。 积分器将整合平均发射机输出电压和参考电压随时间的差异。 积分差值被反馈给发射机以偏置发射机。

    Data receiver including a transconductance amplifier
    3.
    发明申请
    Data receiver including a transconductance amplifier 有权
    数据接收机包括跨导放大器

    公开(公告)号：US20060215787A1

    公开(公告)日：2006-09-28

    申请号：US11091227

    申请日：2005-03-28

    申请人： Zuoguo Wu ,  Feng Chen

    发明人： Zuoguo Wu ,  Feng Chen

    IPC分类号： H04L27/00

    CPC分类号： H04L27/0002 ,  H03F3/45183 ,  H03F3/45968

    摘要： According to one embodiment, a system, apparatus, and method for receiving high-speed signals using a receiver with a transconductance amplifier is presented. The apparatus comprises a transconductance amplifier to receive input voltage derived from an input signal, a clocked current comparator to receive output current from the transconductance amplifier, and a storage element to receive a binary value from the clocked current comparator.

    摘要翻译： 根据一个实施例，提出了一种使用具有跨导放大器的接收机来接收高速信号的系统，装置和方法。 该装置包括跨导放大器以接收从输入信号导出的输入电压，时钟电流比较器以接收来自跨导放大器的输出电流，以及存储元件以从时钟电流比较器接收二进制值。

    Adaptive termination for optimum signal detection
    4.
    发明授权
    Adaptive termination for optimum signal detection 有权
    用于最佳信号检测的自适应终端

    公开(公告)号：US07102381B2

    公开(公告)日：2006-09-05

    申请号：US10879513

    申请日：2004-06-29

    申请人： Feng Chen ,  Qiang Zhang ,  Zuoguo Wu

    发明人： Feng Chen ,  Qiang Zhang ,  Zuoguo Wu

    IPC分类号： H03K17/16 ,  H03K19/003 ,  H03H9/00 ,  H03B11/00

    CPC分类号： H04L25/0278 ,  H04L25/0292

    摘要： An integrated circuit includes a number of terminals to transfer signals. Each of the terminals has an adjustable termination impedance. The integrated circuit also includes a control circuit coupled to the terminals to adjust the value of the termination impedance of each of the terminals to improve signal detection at the terminals.

    摘要翻译： 集成电路包括用于传送信号的多个端子。 每个终端具有可调节的终端阻抗。 集成电路还包括耦合到端子的控制电路，以调整每个端子的端接阻抗的值，以改善端子处的信号检测。

    Adaptive termination for optimum signal detection
    5.
    发明申请
    Adaptive termination for optimum signal detection 有权
    用于最佳信号检测的自适应终端

    公开(公告)号：US20050285621A1

    公开(公告)日：2005-12-29

    申请号：US10879513

    申请日：2004-06-29

    申请人： Feng Chen ,  Qiang Zhang ,  Zuoguo Wu

    发明人： Feng Chen ,  Qiang Zhang ,  Zuoguo Wu

    IPC分类号： H03K19/003 ,  H04L25/02

    CPC分类号： H04L25/0278 ,  H04L25/0292

    摘要： An integrated circuit includes a number of terminals to transfer signals. Each of the terminals has an adjustable termination impedance. The integrated circuit also includes a control circuit coupled to the terminals to adjust the value of the termination impedance of each of the terminals to improve signal detection at the terminals.

    摘要翻译： 集成电路包括用于传送信号的多个端子。 每个终端具有可调节的终端阻抗。 集成电路还包括耦合到端子的控制电路，以调整每个端子的端接阻抗的值，以改善端子处的信号检测。

    Switch portable dock
    7.
    外观设计
    Switch portable dock 有权

    公开(公告)号：USD998609S1

    公开(公告)日：2023-09-12

    申请号：US29887604

    申请日：2023-03-22

    申请人： Feng Chen

    设计人： Feng Chen

    摘要： FIG. 1 is a front, top perspective view of a switch portable dock showing my new design.
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left side view thereof;
    FIG. 5 is a right side view thereof;
    FIG. 6 is a top view thereof;
    FIG. 7 is a bottom view thereof;
    FIG. 8 is a rear, bottom perspective view; and,
    FIG. 9 is a front perspective view thereof, showing the switch portable dock in an open state of use.
    The broken lines in the drawings depict portions of the switch portable dock that form no part of the claimed design.

    Clock and data recovery circuit and parallel output circuit
    10.
    发明授权
    Clock and data recovery circuit and parallel output circuit 有权
    时钟和数据恢复电路和并行输出电路

    公开(公告)号：US08934591B2

    公开(公告)日：2015-01-13

    申请号：US13727849

    申请日：2012-12-27

    申请人： Lianliang Tai ,  Guangren Li ,  Feng Chen

    发明人： Lianliang Tai ,  Guangren Li ,  Feng Chen

    IPC分类号： H04L7/00 ,  H04L7/033

    CPC分类号： H04L7/0012 ,  H04L7/0338

    摘要： The present invention provides a clock and data recovery circuit, including an n-phase clock, a sampling and edge detection unit, an edge determination unit, a clock picking unit and a data picking unit. The sampling and edge detection unit performs spaced sampling on the input serial data using the n-phase clock, and performs edge detection and resampling on the sampled data. The edge determination unit filters the resampled data by the counting units, and obtains the positions of the edges of the serial data according to the counting result of the counting units. The clock picking unit selects a clock from the n clocks that is the farthest away from the edges as the recovered clock. The data picking unit obtains the recovered data according to the recovered clock. The present invention also provides a parallel output circuit.

    摘要翻译： 本发明提供一种包括n相时钟，采样和边缘检测单元，边缘确定单元，时钟采集单元和数据采集单元的时钟和数据恢复电路。 采样和边沿检测单元使用n相时钟对输入串行数据执行间隔采样，并对采样数据执行边沿检测和重采样。 边缘确定单元通过计数单元对重采样数据进行滤波，并根据计数单元的计数结果获得串行数据的边沿的位置。 时钟采集单元从距离边缘最远的n个时钟选择时钟作为恢复时钟。 数据采集​​单元根据恢复的时钟获得恢复的数据。 本发明还提供一种并行输出电路。