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    Fin on silicon-on-insulator
    1.
    发明授权
    Fin on silicon-on-insulator 有权

    公开(公告)号：US12261215B2

    公开(公告)日：2025-03-25

    申请号：US17649184

    申请日：2022-01-27

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Hong Yu ,  Haiting Wang ,  Zhenyu Hu

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

    Abstract: A structure is provided, the structure may include an active layer arranged over a buried oxide layer, the active layer having a top surface. The top surface of the active layer may have a first portion and a second portion. A barrier stack may be arranged over the first portion of the top surface of the active layer. The barrier stack may include a barrier layer. The second portion of the top surface of the active layer may be adjacent to the barrier stack. A fin may be spaced from the first portion of the top surface of the active layer by the barrier stack, the fin having a first side surface, a second side surface opposite to the first side surface and a top surface. A dielectric layer may be arranged on the first side surface, the second side surface and the top surface of the fin, and the second portion of the top surface of the active layer. A metal layer may be arranged over the dielectric layer.

    System and method employing power-optimized timing closure
    2.
    发明授权
    System and method employing power-optimized timing closure 有权

    公开(公告)号：US12260163B2

    公开(公告)日：2025-03-25

    申请号：US17679178

    申请日：2022-02-24

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Mahbub Rashed

    IPC: G06F30/39 ,  G06F30/392 ,  G06F30/398 ,  G06F111/04 ,  G06F111/20

    Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

    Voltage-controlled oscillator with tunable tail harmonic filter
    3.
    发明授权
    Voltage-controlled oscillator with tunable tail harmonic filter 有权

    公开(公告)号：US12249959B1

    公开(公告)日：2025-03-11

    申请号：US18484504

    申请日：2023-10-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Qiao Yang ,  Chi Zhang

    IPC: H03B5/12 ,  H03B5/04 ,  H03B5/36

    Abstract: Disclosed is a voltage-controlled oscillator (VCO) including at least an inductor-capacitor (LC) resonant circuit (including varactors that receive a variable input voltage), cross-coupled transistors connected to the LC resonant circuit, and an LC filter connected to a shared source node of the cross-coupled transistors. The cross-coupled transistors can have back gates connected to receive a variable back gate bias voltage (Vbg), which is dependent on Vin to ensure that an optimal relationship between the oscillating frequency (ω0) of the LC resonant circuit and the resonant frequency (ω1) of the LC filter is continuously maintained to minimize phase noise. For example, if Vin is increased to increase varactor capacitance and, thereby decrease ω0, then Vbg is also increased, thereby increasing the voltage (Vs-s) and the capacitance (Cs-s) on the shared source node connected to the LC filter, decreasing ω1, and maintaining an optimal relationship of ω0=ω1/2.

    STATIC RANDOM ACCESS MEMORY (SRAM) CELL WITH VARIABLE TOGGLE THRESHOLD VOLTAGE AND MEMORY CIRCUIT INCLUDING SRAM CELLS
    5.
    发明申请
    STATIC RANDOM ACCESS MEMORY (SRAM) CELL WITH VARIABLE TOGGLE THRESHOLD VOLTAGE AND MEMORY CIRCUIT INCLUDING SRAM CELLS 有权

    公开(公告)号：US20250078913A1

    公开(公告)日：2025-03-06

    申请号：US18459530

    申请日：2023-09-01

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Xuemei Hui ,  Shafiullah Syed ,  Qiao Yang ,  Wei Zhao

    IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

    Abstract: A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).

    INTEGRATED CIRCUIT WITH FINFET WITH SHORTER AND NARROWER FIN UNDER GATE ONLY
    10.
    发明申请
    INTEGRATED CIRCUIT WITH FINFET WITH SHORTER AND NARROWER FIN UNDER GATE ONLY 有权

    公开(公告)号：US20250040237A1

    公开(公告)日：2025-01-30

    申请号：US18358157

    申请日：2023-07-25

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Vitor A. Vulcano Rossi ,  Anton V. Tokranov ,  Hong Yu ,  David C. Pritchard

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66

    Abstract: An integrated circuit includes a fin having a height and a width under a gate of a selected fin-type field effect transistor (FinFET) that is less than the height and width along a remainder of the fin including under gates and for source/drain regions of other FinFETs. The IC includes a first FinFET having a first gate over a fin having a first height and a first width under the first gate, and a second FinFET in the fin adjacent to the first FinFET. The second FinFET has a second gate over the fin, and the fin has, under the second gate only, a second height less than the first height and a second width less than the first width. The resulting reduced channel height and width for the second FinFET increases gate control and reduces gate leakage, which is beneficial for ultra-low current leakage (ULL) devices.

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