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公开(公告)号：US12126350B2
公开(公告)日：2024-10-22
申请号：US17990737
申请日：2022-11-21
发明人： Ting-Hao Wang , Hui-Wen Tsai , Shih-Chun Lo
CPC分类号： H03M1/0604
摘要： A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.
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公开(公告)号：US20240152418A1
公开(公告)日：2024-05-09
申请号：US17982538
申请日：2022-11-08
发明人： Igor Elkanovich , Yung-Sheng Fang , Pei Yu , Chang-Ming Liu
IPC分类号： G06F11/07
CPC分类号： G06F11/0772 , G06F11/0754
摘要： A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.
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公开(公告)号：US11973511B2
公开(公告)日：2024-04-30
申请号：US17817636
申请日：2022-08-04
发明人： Ting-Hao Wang , Hsin-Han Han
CPC分类号： H03M1/1023 , H03M1/0636 , H03M1/1215 , H03M1/126
摘要： An analog-to-digital converting device includes N-stage first analog-to-digital converters (ADCs), a second ADC, a first calibration circuit, a data recovery circuit and an output circuit. The N-stage first ADCs has a first sampling frequency that is (N+1)/N times of a second sampling frequency, and converts an input signal into first quantized outputs. The second ADC has the second sampling frequency, and converts the input signal into a second quantized output. The first calibration circuit calibrates offsets of the first quantized outputs and the second quantized output to generate third quantized outputs and a fourth quantized output. The data recovery circuit outputs, by the second sampling frequency, one of the third quantized outputs as a fifth quantized output, and subtracts the fifth quantized output from the fourth quantized output to generate output data. The output circuit generates an output signal according to the third quantized outputs and the output data.
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公开(公告)号：US20240072772A1
公开(公告)日：2024-02-29
申请号：US17899623
申请日：2022-08-31
发明人： Bi-Yang Li , Igor Elkanovich , Hung-Yi Chang , Shih-Cheng Kao
CPC分类号： H03K3/012 , G06F1/10 , H03K5/14 , H03L7/0812 , H03K2005/00019
摘要： An interface device and a signal transceiving method thereof are provided. The interface device includes a slave circuit and a master circuit. The slave circuit is coupled to the master circuit and includes a first programmable delay line, a first output clock generator, and a first phase detector. The first programmable delay line provides a first adjusting delay amount according to a first adjust signal, and generates a first delayed clock signal by delaying a first clock signal according to the first adjusting delay amount. The first output clock generator generates a second clock signal according to the first delayed clock signal. The first phase detector detects a phase difference of the first clock signal and the second clock signal to generate first phase lead or lag information. The first adjust signal is generated according to the first phase lead or lag information.
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5.发明授权公开(公告)号：US11699683B2
公开(公告)日：2023-07-11
申请号：US17037753
申请日：2020-09-30
发明人： Igor Elkanovich , Amnon Parnass , Pei Yu , Li-Ken Yeh , Yung-Sheng Fang , Sheng-Wei Lin , Tze-Chiang Huang , King Ho Tam , Ching-Fang Chen
IPC分类号： H01L25/065 , H04L69/08 , G06F13/40 , H04L12/66
CPC分类号： H01L25/0657 , G06F13/409 , G06F13/4068 , H04L12/66 , H04L69/08 , H01L2224/16145
摘要： A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.
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公开(公告)号：US11658091B2
公开(公告)日：2023-05-23
申请号：US17815950
申请日：2022-07-29
发明人： Jia-Liang Chen , Chi-Ming Yang , Yen-Chao Lin
IPC分类号： H01L23/367 , H01L23/00 , H01L21/48 , H01L23/373 , H01L21/56 , H01L23/31
CPC分类号： H01L23/3675 , H01L21/4882 , H01L21/563 , H01L23/3185 , H01L23/3192 , H01L23/3735 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/92 , H01L24/81 , H01L2224/13025 , H01L2224/16145 , H01L2224/17181 , H01L2224/17519 , H01L2224/32145 , H01L2224/33181 , H01L2224/33519 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815 , H01L2224/92125 , H01L2224/92225 , H01L2224/92242 , H01L2924/10253 , H01L2924/10272
摘要： A manufacturing method of a semiconductor packaging device is provided, and the manufacturing method includes steps as follows. A working chip is soldered on one surface of a wiring board so that an working circuit inbuilt inside a chip body of the working chip is electrically connected to the wiring board. A silicon thermal conductivity element is soldered on one surface of a heat-dissipating metal lid. The heat-dissipating metal lid is fixedly covered on the wiring board such that the silicon thermal conductivity element is sandwiched between the chip body and the heat-dissipating metal lid, and the silicon thermal conductivity element is electrically isolated from the working circuit of the chip body and the wiring board.
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公开(公告)号：US11630479B2
公开(公告)日：2023-04-18
申请号：US16921950
申请日：2020-07-07
发明人： Tse-Wei Wu , Chen-Yuan Kao , Min-Hsiu Tsai
IPC分类号： G06F1/10
摘要： An apparatus for adjusting skew of circuit signal and an adjusting method thereof are provided. The adjusting method includes: providing a controller for executing: based on each of a plurality of clock signals, dividing a circuit to generate a plurality of circuit partitions according to a netlist of the circuit; grouping the circuit partitions to respectively generate a plurality of circuit groups; identifying adjacent states of layout areas of the circuit groups; and, adjusting a skew value of each of the circuit groups according to the adjacent states.
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公开(公告)号：US20230046865A1
公开(公告)日：2023-02-16
申请号：US17455013
申请日：2021-11-15
发明人： Chen-Fa TSAI , Che-Li LIN , Chia-Min LIN , Chung-Wei HUANG , Liang-Chi ZANE
IPC分类号： G06F30/392 , G06F30/3947
摘要： A placement method for integrated circuit design is provided. Each net is considered as a soft module. The net will receive a larger penalty if it covers more routing congested regions. Therefore, it is easier to move the nets away from routing congested regions. In addition, to relieve local congestion, a novel inflation method is proposed to expand the area of a cluster according to its internal connectivity intensity and routing congestion occupied by the cluster. Accordingly, it can get better routability and wirelength.
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公开(公告)号：US11569220B2
公开(公告)日：2023-01-31
申请号：US16726829
申请日：2019-12-25
发明人： Wen-Tai Wang
IPC分类号： H02H9/04 , H01L27/02 , H01L29/861
摘要： An electrostatic discharge (ESD) protection device includes a first clamping circuit, a second clamping circuit, and a diode circuit. The first clamping circuit is coupled between a first power rail and a second power rail. The second clamping circuit is coupled between a third power rail and the second power rail. The diode circuit is configured to steer an ESD current from an input/output pad to at least one of the first clamping circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage.
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公开(公告)号：US20220321135A1
公开(公告)日：2022-10-06
申请号：US17447812
申请日：2021-09-15
发明人： Yu-Chu CHEN , Hsin-Han HAN , Wen-Juh KANG
摘要： An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a skew adjusting circuit. The ADC circuits convert an input signal according to clock signals, to generate first quantized outputs. The calibration circuit calibrates the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes an estimating circuit and a feedback circuit. The estimating circuit analyzes the second quantized outputs to generate detection signals, wherein the detection signals are related to time difference information of the clock signals. The skew adjusting circuit outputs the detection signals as adjustment signals, wherein the adjustment signals are configured to reduce a clock skew of the ADC circuits. The feedback circuit analyzes the detection signals generated by the estimating circuit, to generate a feedback signal to the estimating circuit, wherein the estimating circuit is configured to adjust the detection signals according to the feedback signal.
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