公开(公告)号：US5694541A

公开(公告)日：1997-12-02

申请号：US546347

申请日：1995-10-20

申请人： John D. Service ,  Walter A. Jones, Jr. ,  Richard Urmston ,  Arthur J. Beaverson ,  Charles J. Horvath ,  Matthew A. Trask ,  John T. Vachon ,  Jeffrey D. Carter

发明人： John D. Service ,  Walter A. Jones, Jr. ,  Richard Urmston ,  Arthur J. Beaverson ,  Charles J. Horvath ,  Matthew A. Trask ,  John T. Vachon ,  Jeffrey D. Carter

IPC分类号： G06F11/20 ,  G06F11/273 ,  G06F11/30 ,  H04L29/14 ,  G06F15/02

CPC分类号： G06F11/3006 ,  G06F11/3055 ,  H04L69/40 ,  G06F11/16 ,  G06F11/2294 ,  G06F11/2736

摘要： A console terminal arrangement is disclosed for use in connection with a fault-tolerant computer system including a plurality of processing modules, at least some of the processing modules including an operator input/output interface for receiving operator input from an operator input device and operator display output on an operator display device. The console terminal arrangement facilitates management of all of the processing modules by a single operator from a single location. The arrangement includes a console terminal and a plurality of processing module interfaces interconnected by a network. The console terminal includes an operator input device and an operator display device, and generates operator input messages including processing module management information generated by the operator input device in response to inputs provided by an operator and an address identifying one of the processing modules to be managed by the console terminal. The console terminal further generates and displays video images in response to video image data received in messages from the processing modules. Each processing module interface receives operator input messages generated by the console terminal which include an address identifying the processing module connected to the processing module interface and provide the processing module management information to the operator input/output interface to control the processing module. In addition, each processing module interface receives video information from the associated processing module's operator input output device and generates a message including the video information and an address identifying the console terminal. The network carries messages generated by the console terminal and the processing module interfaces in accordance with the addresses contained in the respective messages.

摘要翻译： 公开了一种用于与包括多个处理模块的容错计算机系统结合使用的控制台终端装置，至少一些处理模块包括操作员输入/输出接口，用于从操作员输入装置接收操作者输入和操作者显示 在操作者显示设备上输出。 控制台终端装置便于单个操作员从单个位置管理所有处理模块。 该装置包括控制台终端和由网络互连的多个处理模块接口。 控制终端包括操作员输入装置和操作者显示装置，并且响应于由操作者提供的输入和识别要管理的处理模块之一的地址，生成包括由操作者输入装置产生的处理模块管理信息的操作者输入消息 由控制台终端。 控制台终端还响应于在处理模块的消息中接收的视频图像数据，生成和显示视频图像。 每个处理模块接口接收由控制台终端产生的操作员输入消息，其包括标识连接到处理模块接口的处理模块的地址，并将处理模块管理信息提供给操作员输入/输出接口以控制处理模块。 此外，每个处理模块接口从相关联的处理模块的操作员输入设备接收视频信息，并产生包括视频信息和标识控制台终端的地址的消息。 该网络根据包含在相应消息中的地址携带由控制台终端和处理模块接口产生的消息。

公开(公告)号：US5559459A

公开(公告)日：1996-09-24

申请号：US366414

申请日：1994-12-29

申请人： Paul R. Back ,  Paul R. Carlin ,  Joseph M. Lamb

发明人： Paul R. Back ,  Paul R. Carlin ,  Joseph M. Lamb

IPC分类号： G06F1/04 ,  G06F11/00 ,  G06F11/18 ,  H03K19/00

CPC分类号： G06F11/1604 ,  G06F1/04 ,  G06F11/18

摘要： A clock signal generation arrangement for generating clocking signals for use in a fault-tolerant computer system generates a timing signal in response to a common clock signal. The clock signal generation arrangement comprises a system clock signal generator and a clock signal recovery circuit interconnected by a plurality of clock signal transfer lines. The system clock signal generator generates, in response to a common clock signal, a plurality of system clock signals preferably of uniform frequency and phase for transmission over a like plurality of clock signal transfer lines. The clock signal recovery circuit receives the system clock signals from the clock signal transfer lines and generates a unitary timing signal. The clock signal recovery circuit includes a voting circuit, a latch circuit and a latch control circuit. The voting circuit generates a voted clock signal having signal transitions that are generally aligned with transitions of a majority of the system clock signals. The latch circuit has alternating set and reset conditions in response to transitions of the voted clock signal, and generates the timing signal to have transitions corresponding to the latch circuit's respective set and reset conditions. Finally, the latch control circuit inhibits the latch circuit from transitioning between its set and reset conditions for a selected time period after a previous transition therebetween, so that the latch circuit will be insensitive to noise in the voted clock signal following such a transition.

摘要翻译： 用于产生在容错计算机系统中使用的时钟信号的时钟信号产生装置响应于公共时钟信号产生定时信号。 时钟信号产生装置包括由多个时钟信号传输线互连的系统时钟信号发生器和时钟信号恢复电路。 系统时钟信号发生器响应于公共时钟信号产生多个系统时钟信号，优选地具有均匀的频率和相位，以在相同的多个时钟信号传输线上传输。 时钟信号恢复电路从时钟信号传输线接收系统时钟信号，并产生一个统一的定时信号。 时钟信号恢复电路包括一个投票电路，一个锁存电路和一个锁存控制电路。 投票电路产生具有通常与大多数系统时钟信号的转变对准的信号转换的投票时钟信号。 锁存电路响应于投票时钟信号的转变而具有交替的置位和复位条件，并且产生定时信号以使其对应于锁存电路的相应设置和复位条件。 最后，锁存控制电路在其之间的转换之后的选定时间段内禁止锁存电路在其设定和复位条件之间转换，使得锁存电路对这种转换后的投票时钟信号中的噪声不敏感。

公开(公告)号：US5379381A

公开(公告)日：1995-01-03

申请号：US743992

申请日：1991-08-12

申请人： Joseph M. Lamb

发明人： Joseph M. Lamb

IPC分类号： G06F13/12 ,  G06F13/28 ,  G06F13/32 ,  G06F13/00

CPC分类号： G06F13/28 ,  G06F13/32

摘要： An I/O controller for transferring data between a host processor and one or more I/O units. The controller interleaves processor command transfers (PIO) in the midst of direct memory access (DMA) transfers without repeated data moves. DMA transfers are suspended temporarily during the priority PIO transfer. An interrupt Scanner, for scanning the various I/O units, is also prioritized with respect to DMA and PIO transfers.

摘要翻译： 用于在主处理器和一个或多个I / O单元之间传送数据的I / O控制器。 控制器在直接存储器访问（DMA）传输中交错处理器命令传输（PIO），而不会重复数据移动。 在优先PIO传输期间，DMA传输暂时暂停。 用于扫描各种I / O单元的中断扫描器也相对于DMA和PIO传输优先。

公开(公告)号：US4939643A

公开(公告)日：1990-07-03

申请号：US79223

申请日：1987-07-29

申请人： William L. Long ,  Robert F. Wambach ,  Kurt F. Baty ,  Joseph M. Lamb

发明人： William L. Long ,  Robert F. Wambach ,  Kurt F. Baty ,  Joseph M. Lamb

IPC分类号： G06F13/00 ,  G06F1/04 ,  G06F3/00 ,  G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F13/36 ,  G06F13/42

CPC分类号： G06F11/2017 ,  G06F11/0745 ,  G06F11/0793 ,  G06F11/1402 ,  G06F11/1604 ,  G06F11/1625 ,  G06F11/2005 ,  G06F11/2007 ,  G06F11/22 ,  G06F13/423 ,  G06F1/04 ,  G06F11/10 ,  G06F11/1629 ,  G06F11/1666 ,  G06F11/20

摘要： A fault-tolerant digital data processor includes a peripheral device controller for communicating with one or more peripheral devices over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing information. Each peripheral device includes a device interface for transferring information signals between the associated peripheral device and the peripheral bus. The peripheral device controller includes a strobe element connected with the first and second input/output buses for transmitting thereon duplicative, synchronous and simultaneous strobe signals. These strobe signals define successive timing intervals for information transfers along the peripheral bus. Information transfers are normally effected by the transmission of duplicate information signals synchronously and simultaneously on the first and second input/output buses. A transfer cycle element includes a scanner cycle element to determine an operational state of at least one of the peripheral devices connected to the peripheral bus; a command cycle element for executing a command cycle for controlling operation of an attached peripheral device; a read cycle element for effecting the transfer of data signals from the peripheral device to the input/output controller; and a write cycle element for transferring data signals from the input/output controller an attached peripheral device.

摘要翻译： 容错数字数据处理器包括外围设备控制器，用于通过具有第一和第二输入/输出总线的外围设备总线与一个或多个外围设备通信，每个外围设备总线承载数据，地址，控制和定时信息。 每个外围设备包括用于在相关联的外围设备和外围总线之间传送信息信号的设备接口。 外围设备控制器包括与第一和第二输入/输出总线连接的选通元件，用于在其上传输重复的，同步的和同时的选通信号。 这些选通信号定义了沿着外围总线的信息传输的连续定时间隔。 信息传送通常通过在第一和第二输入/输出总线上同步并同时传输重复信息信号来实现。 转移循环元件包括扫描器循环元件，用于确定连接到外围总线的至少一个外围设备的操作状态; 用于执行用于控制附接的外围设备的操作的命令循环的命令循环元件; 用于实现数据信号从外围设备传送到输入/输出控制器的读周期元件; 以及用于从附加的外围设备的输入/输出控制器传送数据信号的写周期元件。

公开(公告)号：US4866604A

公开(公告)日：1989-09-12

申请号：US227471

申请日：1988-08-01

申请人： Robert Reid

发明人： Robert Reid

IPC分类号： G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G11C29/00

CPC分类号： G06F11/165 ,  G06F11/1616 ,  G06F11/1641 ,  G06F11/167 ,  G06F11/22 ,  G11C29/74 ,  G06F11/10 ,  G06F11/1625 ,  G06F11/2015

摘要： A digital data processing apparatus utilizes a common bus structure for transferring information between functional units, including a processing unit, a peripheral control unit, and first and second memory units. Unit-to-unit information transfers are executed on the bus structure by pipelining signals representative of a transfer cycle that occurs during plural timing intervals and includes plural phases, where the phases of one cycle are non-overlapping and occur in sequence in different respective timing intervals of the transfer cycle. A signalling element periodically generates a first signal indicative the necessity to refresh at least one dynamic memory element in the first memory unit. A memory refresh element normally responds to that first signal for executing a memory refresh cycle during at least one timing interval common to first and second pipelined transfer cycles. A signal is generated indicating the onset of the memory refresh cycle. A memory update element can respond to the update cycle for transferring information from the first memory unit to the second memory unit during a timing interval common to first and second pipelined transfer cycles. The update element generates a signal indicating of the onset of the update cycle.

摘要翻译： 数字数据处理装置利用公共总线结构在包括处理单元，外围控制单元以及第一和第二存储器单元的功能单元之间传送信息。 通过流水线表示在多个定时间隔期间发生的传送周期的信号，在总线结构上执行单元到单元信息传输，并且包括多个相位，其中一个周期的相位不重叠并且在不同的相应定时中依次发生 传送周期的间隔。 信令元件周期性地产生指示刷新第一存储器单元中的至少一个动态存储器元件的必要性的第一信号。 存储器刷新元件通常在第一和第二流水线传输周期共同的至少一个定时间隔期间响应于该第一信号用于执行存储器刷新周期。 产生指示存储器刷新周期开始的信号。 存储器更新元件可以响应于在第一和第二流水线传输周期共同的定时间隔期间将信息从第一存储器单元传送到第二存储器单元的更新周期。 更新元件产生指示更新周期开始的信号。

公开(公告)号：US4486826A

公开(公告)日：1984-12-04

申请号：US307524

申请日：1981-10-01

申请人： Kenneth T. Wolff ,  Joseph E. Samson ,  Kurt F. Baty

发明人： Kenneth T. Wolff ,  Joseph E. Samson ,  Kurt F. Baty

IPC分类号： G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/374 ,  G06F15/16 ,  G06F15/06

CPC分类号： G06F11/1625 ,  G06F11/1641 ,  G06F11/2007 ,  G06F13/374 ,  G06F11/10 ,  G06F11/20

摘要： A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

摘要翻译： 容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。 在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。 错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。 计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。 具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。 模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

公开(公告)号：US5815649A

公开(公告)日：1998-09-29

申请号：US546234

申请日：1995-10-20

申请人： David A. Utter ,  Susan J. Lo Verso ,  Laurie E. Friedman ,  Steven Haid ,  Gregory S. LeBlanc ,  Paul H. Hansen

发明人： David A. Utter ,  Susan J. Lo Verso ,  Laurie E. Friedman ,  Steven Haid ,  Gregory S. LeBlanc ,  Paul H. Hansen

IPC分类号： G06F11/14 ,  G06F11/20 ,  G01F11/08

CPC分类号： G06F11/2071 ,  G06F11/2064 ,  G06F11/1471 ,  G06F11/2082

摘要： A fault-tolerant computer system comprises a plurality of processing nodes and a plurality of storage nodes interconnected by a network. The processing nodes perform processing operations in connection with user-generated processing requests. The processing nodes, in connection with processing a processing request, generate storage and retrieval requests for transmission to the storage node to enable storage of data thereon and retrieval of data therefrom. The storage nodes store data in at least one replicated partition group comprising a plurality of replicated partitions distributed across the storage nodes. A storage node, on receiving a retrieval request from a processing node provide the requested data to the processing node. In addition, on receiving a storage request from a processing node, a storage node initiates an update operation to update all of the replicated partitions in the replicated partition group. Following correction of a malfunction or failure of a storage node, partitions maintained by the malfunctioning or failed storage node can be recovered by use of the other members of the replicated partition group.

摘要翻译： 容错计算机系统包括多个处理节点和由网络互连的多个存储节点。 处理节点结合用户生成的处理请求执行处理操作。 处理节点结合处理处理请求，生成存储和检索请求以传送到存储节点，以便能够存储数据并从中检索数据。 存储节点将数据存储在包括分布在存储节点上的多个复制分区的至少一个复制分区组中。 存储节点在从处理节点接收到检索请求时，向处理节点提供所请求的数据。 此外，在从处理节点接收到存储请求时，存储节点发起更新操作以更新复制分区组中的所有复制分区。 在修复存储节点的故障或故障之后，可以通过使用复制分区组的其他成员来恢复由故障或故障存储节点维护的分区。

公开(公告)号：US5555372A

公开(公告)日：1996-09-10

申请号：US360414

申请日：1994-12-21

申请人： Mark D. Tetreault ,  Charles J. Horvath ,  William I. Leavitt

发明人： Mark D. Tetreault ,  Charles J. Horvath ,  William I. Leavitt

IPC分类号： G06F11/20 ,  G06F11/14 ,  G06F11/30

CPC分类号： G06F11/2007

摘要： A bus device (10) the communicates with other bus devices (12, 13) on a communication channel (14) that includes a plurality of duplicated information buses (16, 17) selectively assumes bus-selection states in which it uses information from one or the other of the buses (16, 17). It also monitors the buses (16, 17) for errors in the information that the buses (16, 17) carry, and it broadcasts an error signal over other lines (18) of the communications channel (14) in response to detection of such an error, but only if an error occurs in information on the bus that its current bus-selection state designates. On the other hand, when an error-broadcast signal indicating an error on either bus in the information transmitted by that device (10) appears on the bus, that bus device (10) retransmits the information, regardless of that device's current bus-selection state. Inconsistent operation phasing among bus devices that have assumed different bus-selection states is thereby avoided.

摘要翻译： 总线设备（10）与包括多个复制信息总线（16,17）的通信信道（14）上的其他总线设备（12,13）进行通信，所述通信信道选择性地假定总线选择状态，其中使用来自一个 或其他公共汽车（16,17）。 它还监视总线（16,17）对总线（16,17）携带的信息中的错误，并且响应于这样的检测而在通信信道（14）的其他线路（18）上广播误差信号 一个错误，但只有当总线选择状态指定的总线上的信息发生错误。 另一方面，当在总线上出现指示由该设备（10）发送的信息中的任一总线上的错误的错误广播信号时，该总线设备（10）重新发送信息，而不管该设备的当前总线选择 州。 因此避免了已经采用不同总线选择状态的总线设备之间的不一致的操作定相。

公开(公告)号：US5475860A

公开(公告)日：1995-12-12

申请号：US898157

申请日：1992-06-15

申请人： Carl Ellison ,  Randy Sybel ,  William D. Snapper ,  Jonathan West

发明人： Carl Ellison ,  Randy Sybel ,  William D. Snapper ,  Jonathan West

IPC分类号： G06F13/12 ,  G06F13/28 ,  G06F13/00 ,  G06F13/38

CPC分类号： G06F13/28 ,  G06F13/124

摘要： A digital data processing apparatus has two functional units (e.g., a host processing section and a peripheral device) and a controller for transferring information therebetween. The first functional unit generates a send message descriptor block ("MDB") signal specifying one or more addresses in an associated local memory from which data is to be transferred. The second functional unit generates a receive MDB signal specifying one or more locations in its associated local memory to which data is to be transferred. The controller matches send and receive MDB signals, particularly, those specifying the same logical or virtual channel. Once a match is found, the controller transfers data between the respective memory locations of the first and second functional units. A controller as described above transfers data between the host and peripheral processors by directly accessing data in their respective "memory spaces."

摘要翻译： 数字数据处理装置具有两个功能单元（例如，主机处理部分和外围设备）和用于在其间传送信息的控制器。 第一功能单元生成指定要从其传送数据的相关联的本地存储器中的一个或多个地址的发送消息描述符块（“MDB”）信号。 第二功能单元产生指定在其相关联的本地存储器中要传送数据的一个或多个位置的接收MDB信号。 控制器匹配发送和接收MDB信号，特别是那些指定相同逻辑或虚拟通道的信号。 一旦找到匹配，则控制器在第一和第二功能单元的相应存储器位置之间传送数据。 如上所述的控制器通过直接访问它们各自的“存储器空间中的数据”来在主机和外围处理器之间传送数据。

公开(公告)号：US5367668A

公开(公告)日：1994-11-22

申请号：US23346

申请日：1993-02-26

申请人： Michael A. Pandolfo

发明人： Michael A. Pandolfo

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G11C29/00

CPC分类号： G06F11/00 ,  G06F11/16 ,  G06F11/004 ,  G06F11/0751 ,  G06F11/0757 ,  G06F11/1402 ,  G11C29/88

摘要： An improved method for operating a digital data processing apparatus to provide for fault-tolerant actuation of a functional unit in response to an actuation request includes the steps of: providing the functional unit with a switching section that responds to application of plural switching signals for activating the functional unit; providing first and second processing elements, each normally responding to an actuation request for generating a first set of switching signals, the first set of switching signals including at least one, but not all, of the plural switching signals; outputting the first set of switching signals generated by the first processing element for application to the switching section; synchronizing the first and second processing elements by comparing, with the second processing element, the first set of switching signals generated thereby with those output by the first processing element; generating, after synchronization, with each of the first and second processing elements, a second set of switching signals, the second set of switching signals including at least one, but not all, of the plural switching signals, the first and second subsets of switching signals together making up the plural switching signals; and outputting the second set of switching signals generated by the second processing element for application to the switching section.

摘要翻译： 一种用于操作数字数据处理装置以提供响应于致动请求的功能单元的容错致动的改进方法包括以下步骤：向功能单元提供响应多个切换信号的激活的切换部分 功能单元; 提供第一和第二处理元件，每个处理元件通常响应于用于产生第一组开关信号的致动请求，所述第一组开关信号包括所述多个开关信号中的至少一个但不是全部; 将由所述第一处理元件生成的第一组切换信号输出到所述切换部分; 将第一和第二处理元件与第二处理元件进行比较，由第一处理元件产生的第一组切换信号与由第一处理元件输出的第一组切换信号同步; 在同步之后，与第一和第二处理元件中的每一个产生第二组开关信号，第二组开关信号包括多个开关信号中的至少一个但不是全部，第一和第二开关子集 一起构成多个开关信号的信号; 以及将由所述第二处理元件生成的第二组切换信号输出到所述切换部。