公开(公告)号：US5634079A

公开(公告)日：1997-05-27

申请号：US885805

申请日：1992-05-15

申请人： Clark L. Buxton

发明人： Clark L. Buxton

IPC分类号： G06F9/445 ,  G06F11/14 ,  G06F11/20 ,  G06F3/00

CPC分类号： G06F9/4403 ,  G06F11/1417

摘要： A computer system as provided with an internal flash ROM which includes the BIOS. In the event the flash ROM becomes corrupt, a special purpose interface allows for mode switching of a standard parallel port from a standard peripheral interface, such as a printer interface to a special purpose interface to enable the BIOS to be executed from an external ROM or another computer connected to the parallel port.

摘要翻译： 具有包括BIOS的内部闪存ROM的计算机系统。 在闪存ROM损坏的情况下，专用接口允许将标准并行端口从诸如打印机接口的标准外围接口模式切换到专用接口，以使得能够从外部ROM执行BIOS，或者 另一台计算机连接到并行端口。

公开(公告)号：US5596713A

公开(公告)日：1997-01-21

申请号：US478363

申请日：1995-06-07

申请人： David T. DeRoo ,  Mark D. Nicol ,  David J. DeLisle ,  Saifuddin Fakhruddin ,  Lloyd W. Gauthier ,  Robert A. Kohtz

发明人： David T. DeRoo ,  Mark D. Nicol ,  David J. DeLisle ,  Saifuddin Fakhruddin ,  Lloyd W. Gauthier ,  Robert A. Kohtz

IPC分类号： G06F1/00 ,  G06F9/30 ,  G06F9/32 ,  G06F9/445 ,  G06F9/50 ,  G06F11/00 ,  G06F12/14 ,  G06F21/00 ,  G11C29/00

CPC分类号： G06F9/4401 ,  G06F11/004 ,  G06F12/1433 ,  G06F21/79 ,  G06F9/30101 ,  G06F9/30141 ,  G06F9/32 ,  G06F9/5016 ,  G11C29/88

摘要： An apparatus and method for tracking and interception of instructions as they are presented to the memory, selectively passing harmless data to the device and disallowing the sequences which instruct the device to perform harmful functions, such as self-erase. A software trap is provided to be transparent to the operation of the device and the host system, imposing no harmful timing delays or software overhead. Accordingly, the invention allows the use of standard electrically erasable read-only memories in an application which requires that the device be protected from global erasure. A hardware front end intercepts the software command which is used to globally erase the device. The apparatus receives address signals from the computer system corresponding to the protected peripheral device, receives data signals from the computer system to the protected peripheral device, tracks a predetermined sequence of address and address signals, substitutes at least one of the data signals received with a replacement data signal, and sends a replacement data signal.

摘要翻译： 一种用于在将指令呈现给存储器时跟踪和截取指令的设备和方法，选择性地将无害数据传送到设备，并且禁止指示设备执行有害功能（例如自擦除）的序列。 提供软件陷阱对设备和主机系统的操作是透明的，不会产生有害的定时延迟或软件开销。 因此，本发明允许在需要保护设备免受全局擦除的应用中使用标准的电可擦除只读存储器。 硬件前端拦截用于全局擦除设备的软件命令。 该装置从对应于受保护的外围设备的计算机系统接收地址信号，从计算机系统接收数据信号到受保护的外围设备，跟踪预定的地址和地址信号序列，代替接收到的数据信号中的至少一个 替换数据信号，并发送替换数据信号。

公开(公告)号：USD376355S

公开(公告)日：1996-12-10

申请号：US36156

申请日：1995-03-14

申请人： Peter A. Ojeda, IV

设计人： Peter A. Ojeda, IV

公开(公告)号：US5574866A

公开(公告)日：1996-11-12

申请号：US389559

申请日：1995-02-15

申请人： Jimmy D. Smith ,  Mark D. Nicol ,  Terence P. O'Brien

发明人： Jimmy D. Smith ,  Mark D. Nicol ,  Terence P. O'Brien

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4239

摘要： A control circuit which allows computer systems to modify signal timing relationships in the hardware via programmable ports in the system, thereby allowing timing adjustments to be made without effecting motherboard hardware. The control circuit includes a plurality of delay devices configured to provide a plurality of delays under program control. The control circuit is adapted to extend the duration of a write signal to enable data to be latched, normally on the trailing edge of the write signal to avoid latching invalid data.

摘要翻译： 一种控制电路，其允许计算机系统通过系统中的可编程端口修改硬件中的信号定时关系，从而允许进行时序调整而不影响主板硬件。 控制电路包括被配置为在程序控制下提供多个延迟的多个延迟装置。 控制电路适于延长写入信号的持续时间，以使数据通常在写入信号的后沿被锁存，以避免锁存无效数据。

公开(公告)号：US5363486A

公开(公告)日：1994-11-08

申请号：US91462

申请日：1993-07-13

申请人： Anthony M. Olson ,  Babu Rajaram

发明人： Anthony M. Olson ,  Babu Rajaram

IPC分类号： G06F13/16 ,  G06F13/00 ,  G06F12/00

CPC分类号： G06F13/1642

摘要： A computer system includes a memory capable of storing a plurality of data words, and a central processing unit for outputting data words to be stored in the memory. A method and apparatus for facilitating transfer of the data words from the central processing unit to the memory involve accepting and temporarily storing in a storage portion each data word from the central processing unit and then subsequently storing in the memory each temporarily stored data word, the maximum number of data words which can be temporarily stored being selectively set to one of first and second values which are different.

摘要翻译： 计算机系统包括能够存储多个数据字的存储器，以及用于输出要存储在存储器中的数据字的中央处理单元。 一种用于促进将数据字从中央处理单元传送到存储器的方法和装置，包括接收和临时存储来自中央处理单元的每个数据字的存储部分，然后在存储器中存储每个临时存储的数据字， 可以临时存储的最大数量的数据字被选择性地设置为不同的第一和第二值中的一个。

公开(公告)号：US5353416A

公开(公告)日：1994-10-04

申请号：US999189

申请日：1992-12-30

申请人： Anthony M. Olson

发明人： Anthony M. Olson

IPC分类号： G06F13/364 ,  G06F13/00 ,  G06F13/36

CPC分类号： G06F13/364

摘要： A shared bus arbitration system is disclosed which provides logic allowing multiple processors to co-exist on a common bus. In the present invention, the host processor is isolated from the bus by a posted write array or write buffer. The arbitration system accepts bus lock and cycle signals when the processor writes a locked instruction to the posted write array and provides a bus lock signal to the bus when the locked instructions are written to the bus.

摘要翻译： 公开了一种共享总线仲裁系统，其提供允许多个处理器在公共总线上共存的逻辑。 在本发明中，主处理器通过贴写的写阵列或写缓冲器与总线隔离。 当处理器将已锁定的指令写入发布的写入阵列时，仲裁系统接受总线锁定和周期信号，并且当锁定的指令写入总线时，仲裁系统向总线提供总线锁定信号。

公开(公告)号：US5303171A

公开(公告)日：1994-04-12

申请号：US865048

申请日：1992-04-03

申请人： Steven L. Belt ,  Robert J. Grabon ,  Chandrakant H. Pandya ,  Jiming Sun ,  Neysa K. Terry-Gray

发明人： Steven L. Belt ,  Robert J. Grabon ,  Chandrakant H. Pandya ,  Jiming Sun ,  Neysa K. Terry-Gray

IPC分类号： G06F1/24 ,  G06F1/32 ,  G06F1/00

CPC分类号： G06F1/324 ,  G06F1/24 ,  G06F1/3203 ,  Y02B60/1217

摘要： A portable computer system includes a housing, a lid supported on the housing for movement between open and closed positions, a keyboard supported on the housing below the lid, and a display provided on the lid. When the lid is opened, the keyboard is accessible and the display is visible, whereas when the lid is closed the keyboard and display are hidden and protected. The computer system includes a processor disposed within the housing and having a first operational mode in which it executes instructions and a second operational mode in which it is in a reduced power suspend state from which it can automatically exit in response to a predetermined condition. The system includes an arrangement responsive to closing of the lid when the processor is in its first operational state for switching the processor to its second operational state.

摘要翻译： 便携式计算机系统包括壳体，支撑在壳体上用于在打开和关闭位置之间运动的盖子，支撑在盖子下方的壳体上的键盘以及设置在盖子上的显示器。 当盖子打开时，键盘可以访问并且显示屏是可见的，而当盖子关闭时，键盘和显示器被隐藏并被保护。 计算机系统包括设置在壳体内的处理器，并且具有第一操作模式，其中它执行指令和第二操作模式，其中它处于能够响应于预定条件自动退出的降低功率暂停状态。 当处理器处于其第一操作状态以便将处理器切换到其第二操作状态时，系统包括响应于关闭盖子的装置。

公开(公告)号：US5297270A

公开(公告)日：1994-03-22

申请号：US17972

申请日：1993-02-12

申请人： Anthony M. Olson

发明人： Anthony M. Olson

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0888

摘要： A system includes a main memory having a plurality of sections which each include a plurality of selectively addressable storage locations, a cache memory, and an accessing arrangement for successively requesting data from respective locations in the main memory. A method and apparatus for controlling the system involve assigning each section of the main memory a changeable status condition which is one of a caching enabled status and a caching disabled status, and inhibiting reading and storing of data by the cache memory when data requested by the accessing unit is in one of the sections of the main memory having the caching disabled status. An alternative method and apparatus for controlling the system involve selective operation in a mode in which data in the cache memory is updated even when reading of data from the cache memory is inhibited.

摘要翻译： 一种系统包括具有多个部分的主存储器，每个部分包括多个可选择寻址的存储位置，高速缓冲存储器和用于从主存储器中的相应位置连续地请求数据的访问装置。 一种用于控制系统的方法和装置，包括：将主存储器的每个部分分配为可缓存状态条件，该可变状态条件是缓存使能状态和缓存禁用状态之一，并且当由所述高速缓冲存储器请求的数据时禁止高速缓冲存储器读取和存储数据 访问单元位于具有缓存禁用状态的主存储器的其中一个区域中。 用于控制系统的替代方法和装置涉及在高速缓冲存储器中的数据被更新的模式中的选择性操作，即使当从高速缓冲存储器读取数据被禁止时，也是如此。

公开(公告)号：US5261083A

公开(公告)日：1993-11-09

申请号：US692371

申请日：1991-04-26

申请人： Todd R. Witkowski ,  Anthony M. Olson ,  Thomas N. Robinson ,  Jimmy D. Smith

发明人： Todd R. Witkowski ,  Anthony M. Olson ,  Thomas N. Robinson ,  Jimmy D. Smith

IPC分类号： G06F3/06 ,  G06F13/28 ,  G06F11/00

CPC分类号： G06F3/0601 ,  G06F13/28 ,  G06F2003/0692

摘要： A system includes a system bus having data lines, an acknowledge line, an enable line, and a control line, a data storage device, a controller circuit, and an arrangement coupling the system bus, controller circuit and data storage device. The system bus can carry out a data transfer cycle in which the acknowledge, enable and control lines are actuated and the controller obtains and checks data from the data storage device and supplies it to data lines of the bus, and a verify cycle in which the acknowledge and enable lines are actuated and the control line is deactuated and the controller obtains and checks data from the storage device but does not supply it to the bus. The controller circuit is capable of operating in different modes, in one of which it forcibly sets a false error indication in response to the verify cycle. In response to the acknowledge line and enable line being simultaneously actuated while the control line remains deactuated throughout a cycle, an arrangement supplies a special signal to the controller circuit so that the controller circuit interprets the cycle as a data transfer cycle and does not set a false error indication.

摘要翻译： 系统包括具有数据线，确认线，使能线和控制线的系统总线，数据存储装置，控制器电路和耦合系统总线，控制器电路和数据存储装置的装置。 系统总线可以执行数据传输周期，其中确认，使能和控制线路被激活，并且控制器从数据存储设备获取和检查数据并将其提供给总线的数据线，以及验证周期，其中 确认和启用线路被激活，并且控制线路被去激活，并且控制器获取并检查来自存储设备的数据，但不将其提供给总线。 控制器电路能够以不同的模式操作，其中一个模式响应验证周期强制设置错误指示。 响应于确认线路和使能线路同时致动，同时控制线路在整个周期内保持停止，这样一种装置向控制器电路提供特殊信号，使得控制器电路将该周期解释为数据传输周期，并且不设置 虚假错误指示。

公开(公告)号：US5253350A

公开(公告)日：1993-10-12

申请号：US555778

申请日：1990-07-19

申请人： Mark J. Foster ,  Babu Rajaram ,  Anthony M. Olson

发明人： Mark J. Foster ,  Babu Rajaram ,  Anthony M. Olson

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0623

摘要： In response to an address decoded in a preselected range, a multiplexer combines translated high order address bits with CPU-generated low order address bits to access random access memory, especially reserved range random access memory. Otherwise, the multiplexer merely combines CPU-generated low order bits with CPU-generated high order address bits to access RAM. An expanded memory specification memory map drives the translator to generate the translated high order address bits. This generates the address for reserved range RAM. RAM contents, normal and reserved range, are available for processing by the CPU.

摘要翻译： 响应于以预选范围解码的地址，多路复用器将转换后的高阶地址位与CPU生成的低位地址位组合以访问随机存取存储器，特别是预留范围随机存取存储器。 否则，多路复用器仅将CPU生成的低位位与CPU生成的高位地址位组合以访问RAM。 扩展的存储器规范存储器映射驱动转换器以产生转换的高位地址位。 这将产生预留范围RAM的地址。 RAM内容，正常和保留范围可供CPU处理。