公开(公告)号：US20140351563A1

公开(公告)日：2014-11-27

申请号：US14365617

申请日：2012-12-17

Applicant: HYPERION CORE INC.

Inventor： Martin Vorbach

IPC: G06F9/30

CPC classification number: G06F9/30189 ,  G06F9/355 ,  G06F9/3885 ,  G06F9/3897

Abstract: The present invention relates to a processor core having an execution unit comprising an arrangement of Arithmetic-Logic-Units, wherein the operation mode of the execution unit is switchable between an asynchronous operation of the Arithmetic-Logic-Units and interconnection between the Arithmetic-Logic-Units such that a signal. from the register file crosses the execution unit and is receipt by the register file in one clock cycle; and wherein a pipelined operation mode of at least one of the Arithmetic-Logic-Units and the interconnection between the Arithmetic-Logic-Units such that a signal requires from the register file through the execution unit back to the register file more than one clock cycles.

Abstract translation: 本发明涉及具有执行单元的处理器核心，该执行单元包括算术逻辑单元的布置，其中执行单元的操作模式可以在算术逻辑单元的异步操作和算术逻辑单元之间的互连之间切换 - 这样一个信号。 寄存器文件通过执行单元，并在一个时钟周期内由寄存器文件接收; 并且其中所述算术逻辑单元中的至少一个和所述算术逻辑单元之间的互连的流水线操作模式使得信号需要从所述寄存器文件通过所述执行单元返回所述寄存器文件多于一个时钟周期 。

公开(公告)号：US10409608B2

公开(公告)日：2019-09-10

申请号：US15891094

申请日：2018-02-07

Applicant: Hyperion Core, Inc.

Inventor： Martin Vorbach ,  Frank May ,  Markus Weinhardt

IPC: G06F9/38 ,  G06F8/41 ,  G06F9/30

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

公开(公告)号：US09898297B2

公开(公告)日：2018-02-20

申请号：US14830704

申请日：2015-08-19

Applicant: Hyperion Core, Inc.

Inventor： Martin Vorbach ,  Frank May ,  Markus Weinhardt

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/45

CPC classification number: G06F9/3836 ,  G06F8/443 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30065 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30134 ,  G06F9/30189 ,  G06F9/381 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

公开(公告)号：US11797474B2

公开(公告)日：2023-10-24

申请号：US17079465

申请日：2020-10-24

Applicant: Hyperion Core, Inc.

Inventor： Martin Vorbach

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0893 ,  G11C8/16 ,  G11C11/412 ,  G06F8/41 ,  G06F12/0877

CPC classification number: G06F15/7839 ,  G06F9/3017 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0893 ,  G06F15/7821 ,  G06F8/4441 ,  G06F8/452 ,  G06F12/0877 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2213/0038 ,  G11C8/16 ,  G11C11/412 ,  Y02D10/00

Abstract: Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.

公开(公告)号：US09672188B2

公开(公告)日：2017-06-06

申请号：US14693793

申请日：2015-04-22

Applicant: Hyperion Core Inc.

Inventor： Martin Vorbach

IPC: G06F9/45 ,  G06F15/78 ,  G06F9/38

CPC classification number: G06F15/7807 ,  G06F8/41 ,  G06F8/4441 ,  G06F8/452 ,  G06F9/3885

Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

公开(公告)号：US20190197015A1

公开(公告)日：2019-06-27

申请号：US16042803

申请日：2018-07-23

Applicant: Hyperion Core, Inc.

Inventor： Martin Vorbach

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F15/7839 ,  G06F8/4441 ,  G06F8/452 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/38 ,  G06F15/7821 ,  G06F2213/0038 ,  G11C8/16 ,  G11C11/412 ,  Y02D10/12 ,  Y02D10/13

Abstract: The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.

公开(公告)号：US09734064B2

公开(公告)日：2017-08-15

申请号：US14791350

申请日：2015-07-03

Applicant: Hyperion Core Inc.

Inventor： Martin Vorbach

IPC: G06F12/08 ,  G06F12/0815 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/0893 ,  G06F12/084

CPC classification number: G06F12/0815 ,  G06F9/526 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0893 ,  G06F2212/271 ,  G06F2212/50 ,  G06F2212/62 ,  Y02D10/13

Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

公开(公告)号：US11687346B2

公开(公告)日：2023-06-27

申请号：US17070689

申请日：2020-10-14

Applicant: Hyperion Core, Inc.

Inventor： Martin Vorbach

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F9/355

CPC classification number: G06F9/3836 ,  G06F9/3001 ,  G06F9/3013 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30138 ,  G06F9/30167 ,  G06F9/325 ,  G06F9/355 ,  G06F9/381 ,  G06F9/383 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3887 ,  G06F9/3889

Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

公开(公告)号：US20210286755A1

公开(公告)日：2021-09-16

申请号：US17079465

申请日：2020-10-24

Applicant: Hyperion Core, Inc.

Inventor： Martin Vorbach

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.

公开(公告)号：US11061682B2

公开(公告)日：2021-07-13

申请号：US15535697

申请日：2015-12-13

Applicant: Martin Vorbach ,  Hyperion Core, Inc.

Inventor： Martin Vorbach

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).