公开(公告)号：US09024544B2

公开(公告)日：2015-05-05

申请号：US13509537

申请日：2010-11-10

申请人： Masayoshi Nagao ,  Tomoya Yoshida ,  Yoichiro Neo

发明人： Masayoshi Nagao ,  Tomoya Yoshida ,  Yoichiro Neo

IPC分类号： H01J3/02 ,  H01J31/12

CPC分类号： H01J3/022 ,  H01J31/127 ,  H01J2203/0208 ,  H01J2203/0228 ,  H01J2329/4604 ,  H01J2329/4626

摘要： In a field emission device, the fundamental cause of spherical aberration in an emitted electron beam trajectory is eliminated or mitigated. An aberration suppressor electrode 31 is provided at a lower vertical position than an extraction gate electrode 13 so its opening inner peripheral edge 31e faces a position near an emitter tip 11tp. The vertical position of the opening inner peripheral edge 31e of the aberration suppressor electrode 31 is made lower than the vertical position of the emitter tip 11tp. An aberration suppressing voltage Vsp is applied to the aberration suppressor electrode 31 that is a lower voltage than the potential of the emitter 11 and controls equipotential lines near the emitter tip 11tp to make them parallel.

摘要翻译： 在场发射器件中，消除或减轻发射的电子束轨迹中球面像差的根本原因。 在比提取栅电极13低的垂直位置处设置像差抑制电极31，使得其开口内周边缘31e面向发射极尖端11tp附近的位置。 使像差抑制电极31的开口内周缘31e的垂直位置比发射极尖端11tp的垂直位置低。 像差抑制电压Vsp被施加到比发射极11的电位低的电压的像差抑制电极31，并且控制发射极尖端11tp附近的等电位线使其平行。

公开(公告)号：US20120229051A1

公开(公告)日：2012-09-13

申请号：US13509537

申请日：2010-11-10

申请人： Masayoshi Nagao ,  Tomoya Yoshida ,  Yoichiro Neo

发明人： Masayoshi Nagao ,  Tomoya Yoshida ,  Yoichiro Neo

IPC分类号： H01J29/46

CPC分类号： H01J3/022 ,  H01J31/127 ,  H01J2203/0208 ,  H01J2203/0228 ,  H01J2329/4604 ,  H01J2329/4626

摘要： In a field emission device, the fundamental cause of spherical aberration in an emitted electron beam trajectory is eliminated or mitigated. An aberration suppressor electrode 31 is provided at a lower vertical position than an extraction gate electrode 13 so its opening inner peripheral edge 31e faces a position near an emitter tip 11tp. The vertical position of the opening inner peripheral edge 31e of the aberration suppressor electrode 31 is made lower than the vertical position of the emitter tip 11tp. An aberration suppressing voltage Vsp is applied to the aberration suppressor electrode 31 that is a lower voltage than the potential of the emitter 11 and controls equipotential lines near the emitter tip 11tp to make them parallel.

摘要翻译： 在场发射器件中，消除或减轻发射的电子束轨迹中球面像差的根本原因。 在比提取栅电极13低的垂直位置处设置像差抑制电极31，使得其开口内周边缘31e面向发射极尖端11tp附近的位置。 使像差抑制电极31的开口内周缘31e的垂直位置比发射极尖端11tp的垂直位置低。 像差抑制电压Vsp被施加到比发射极11的电位低的电压的像差抑制电极31，并且控制发射极尖端11tp附近的等电位线使其平行。

公开(公告)号：US08016630B2

公开(公告)日：2011-09-13

申请号：US12314033

申请日：2008-12-03

申请人： Chi-Tsung Lo ,  Tzung-Han Yang ,  Richard Allan Tuck

发明人： Chi-Tsung Lo ,  Tzung-Han Yang ,  Richard Allan Tuck

IPC分类号： H01J17/49

CPC分类号： H01J9/025 ,  H01J3/021 ,  H01J9/148 ,  H01J29/481 ,  H01J31/127 ,  H01J2203/0228 ,  H01J2329/4626

摘要： A substrate 200 is provided with conductive cathode tracks and a field electron emission material on the tracks. Septa 201 and pillars 202 are provided as raised elements over the emission material. An electrically insulating layer is formed over the emission material and raised elements 201, 202, such that boundary walls are formed in the insulating layer where it contacts the raised elements. The raised elements 201, 202 are then removed, to leave emitter cells and voids for other components, defined by the boundary walls with the insulating layer. A gate electrode is provided over the insulating layer.

摘要翻译： 衬底200在轨道上设置有导电阴极轨道和场电子发射材料。 隔垫201和支柱202在发射材料上设置为凸起元件。 在发射材料和凸起元件201,202上形成电绝缘层，使得边界壁形成在与凸起元件接触的绝缘层中。 然后去除凸起元件201,202，以留下由具有绝缘层的边界壁限定的其他部件的发射极电池和空隙。 在绝缘层上设置栅电极。

公开(公告)号：US08017413B2

公开(公告)日：2011-09-13

申请号：US12450965

申请日：2008-07-01

申请人： Seung Seob Lee ,  Seok Woo Lee ,  Jung A Lee

发明人： Seung Seob Lee ,  Seok Woo Lee ,  Jung A Lee

IPC分类号： H01L21/00

CPC分类号： H01J1/3044 ,  H01J3/022 ,  H01J9/025 ,  H01J31/127 ,  H01J63/02 ,  H01J2201/30415 ,  H01J2201/30453 ,  H01J2203/0228 ,  H01J2329/0418 ,  H01J2329/0444 ,  H01J2329/4626

摘要： Provided is a method for manufacturing a field emission array with a carbon microstructure. The method includes: a photomask attachment step of attaching a photomask with a pattern groove to one surface of a transparent substrate; a photoresist attachment step of attaching a negative photoresist to one surface of the photomask; an exposure step of irradiating light toward the opposite surface of the transparent substrate from the photomask to cure a portion of the negative photoresist with the light irradiated on the negative photoresist through the pattern groove; a developing step of removing an uncured portion of the negative photoresist while leaving the cured portion of the negative photoresist as a microstructure; a pyrolysis step of heating and carbonizing the microstructure thus obtained; and a cathode attachment step of attaching a voltage-supplying cathode to the surface of the transparent substrate on which the microstructure is formed.

摘要翻译： 提供一种制造具有碳微观结构的场致发射阵列的方法。 该方法包括：光掩模附着步骤，其将具有图案凹槽的光掩模附着到透明基板的一个表面; 将负性光致抗蚀剂附着到光掩模的一个表面的光致抗蚀剂附着步骤; 曝光步骤，从所述光掩模向所述透明基板的相对表面照射光，以通过所述图案凹槽照射在所述负性光致抗蚀剂上的光来固化所述负性光致抗蚀剂的一部分; 去除负性光致抗蚀剂的未固化部分同时留下负性光致抗蚀剂的固化部分作为微结构的显影步骤; 对由此获得的微结构进行加热和碳化的热解步骤; 以及将电压供给阴极安装在其上形成微结构的透明基板的表面上的阴极附着步骤。

公开(公告)号：US20110089396A1

公开(公告)日：2011-04-21

申请号：US12450965

申请日：2008-07-01

申请人： Seung Seob Lee ,  Seok Woo Lee ,  Jung A Lee

发明人： Seung Seob Lee ,  Seok Woo Lee ,  Jung A Lee

IPC分类号： H01L29/16 ,  H01L21/28 ,  H01L21/66

CPC分类号： H01J1/3044 ,  H01J3/022 ,  H01J9/025 ,  H01J31/127 ,  H01J63/02 ,  H01J2201/30415 ,  H01J2201/30453 ,  H01J2203/0228 ,  H01J2329/0418 ,  H01J2329/0444 ,  H01J2329/4626

摘要： Provided is a method for manufacturing a field emission array with a carbon microstructure. The method includes: a photomask attachment step of attaching a photomask with a pattern groove to one surface of a transparent substrate; a photoresist attachment step of attaching a negative photoresist to one surface of the photomask; an exposure step of irradiating light toward the opposite surface of the transparent substrate from the photomask to cure a portion of the negative photoresist with the light irradiated on the negative photoresist through the pattern groove; a developing step of removing an uncured portion of the negative photoresist while leaving the cured portion of the negative photoresist as a microstructure; a pyrolysis step of heating and carbonizing the microstructure thus obtained; and a cathode attachment step of attaching a voltage-supplying cathode to the surface of the transparent substrate on which the microstructure is formed.

摘要翻译： 提供一种制造具有碳微观结构的场致发射阵列的方法。 该方法包括：光掩模附着步骤，其将具有图案凹槽的光掩模附着到透明基板的一个表面; 将负性光致抗蚀剂附着到光掩模的一个表面的光致抗蚀剂附着步骤; 曝光步骤，从所述光掩模向所述透明基板的相对表面照射光，以通过所述图案凹槽照射在所述负性光致抗蚀剂上的光来固化所述负性光致抗蚀剂的一部分; 去除负性光致抗蚀剂的未固化部分同时留下负性光致抗蚀剂的固化部分作为微结构的显影步骤; 对由此获得的微结构进行加热和碳化的热解步骤; 以及将电压供给阴极安装在其上形成微结构的透明基板的表面上的阴极附着步骤。

公开(公告)号：US20090140629A1

公开(公告)日：2009-06-04

申请号：US12314033

申请日：2008-12-03

申请人： Chi-Tsung Lo ,  Tzung-Han Yang ,  Richard Allan Tuck

发明人： Chi-Tsung Lo ,  Tzung-Han Yang ,  Richard Allan Tuck

IPC分类号： H01J63/04 ,  H01J9/18

CPC分类号： H01J9/025 ,  H01J3/021 ,  H01J9/148 ,  H01J29/481 ,  H01J31/127 ,  H01J2203/0228 ,  H01J2329/4626

摘要： A substrate 200 is provided with conductive cathode tracks and a field electron emission material on the tracks. Septa 201 and pillars 202 are provided as raised elements over the emission material. An electrically insulating layer is formed over the emission material and raised elements 201, 202, such that boundary walls are formed in the insulating layer where it contacts the raised elements. The raised elements 201, 202 are then removed, to leave emitter cells and voids for other components, defined by the boundary walls with the insulating layer. A gate electrode is provided over the insulating layer.

摘要翻译： 衬底200在轨道上设置有导电阴极轨道和场电子发射材料。 隔垫201和支柱202在发射材料上设置为凸起元件。 在发射材料和凸起元件201,202上形成电绝缘层，使得边界壁形成在与凸起元件接触的绝缘层中。 然后去除凸起元件201,202，以留下由具有绝缘层的边界壁限定的其他部件的发射极电池和空隙。 在绝缘层上设置栅电极。

公开(公告)号：US6010917A

公开(公告)日：2000-01-04

申请号：US725646

申请日：1996-10-15

申请人： James J. Alwan ,  Kevin Tjaden ,  David A. Cathey

发明人： James J. Alwan ,  Kevin Tjaden ,  David A. Cathey

IPC分类号： H01L21/00

CPC分类号： H01J31/127 ,  H01J29/467 ,  H01J3/022 ,  H01J9/148 ,  H01J2203/0228 ,  H01J2203/0232 ,  H01J2329/4626 ,  H01J2329/463

摘要： A method for fabricating microelectronic deices in which an interconnect layer is electrically isolated from large protuberances that project from a lower conductive layer to a desired endpoint of a chemical-mechanical planarization process. The lower conductive layer is covered with an insulating material to form an insulator layer that generally follows the contour of the lower conductive layer and any large protuberances. A highly conductive interconnect material is then deposited over the insulator layer to form an interconnect layer that generally follows the contour of the insulator layer. The interconnect layer may be deposited directly on the insulator layer, or it may be deposited on an intermediate layer between the interconnect layer and the insulator layer. After the upper conductive layer is deposited, the insulator layer and the upper conductive layer are planarized with a chemical-mechanical planarization process to a desired endpoint.

摘要翻译： 一种用于制造微电子器件的方法，其中互连层与从下导电层突出到化学机械平面化工艺的期望端点的大突起电隔离。 下导电层被绝缘材料覆盖以形成通常遵循下导电层和任何大突起的轮廓的绝缘体层。 然后将高度导电的互连材料沉积在绝缘体层上，以形成大致遵循绝缘体层的轮廓的互连层。 互连层可以直接沉积在绝缘体层上，或者它可以沉积在互连层和绝缘体层之间的中间层上。 在沉积上导电层之后，通过化学机械平面化工艺将绝缘体层和上导电层平坦化成期望的端点。