公开(公告)号：US20150138866A1

公开(公告)日：2015-05-21

申请号：US14482402

申请日：2014-09-10

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Atsushi KAWASUMI

IPC分类号： G11C17/18 ,  G11C17/08 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C5/06 ,  G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C11/1673 ,  G11C11/4074 ,  G11C11/417 ,  G11C11/5642 ,  G11C17/08 ,  G11C17/16 ,  G11C29/06 ,  G11C29/42 ,  G11C29/52

摘要： According to an embodiment, a semiconductor memory includes word lines, a plurality of sets of a pair of bit lines, memory cells, a writing/reading circuit, and a word line selection circuit. In a state where inverted data of program data has been written to the memory cells, a stress is applied and the program data is programmed to the memory cells. The writing/reading circuit writes the inverted data of the same program data to a unit memory cell group made of memory cells connected to a set of a pair of bit lines at a time of programming, and reads data from the unit memory cell group by detecting a signal level of the pair of bit lines at a time of reading. The word line selection circuit simultaneously selects and drives two or more word lines of the word lines connected to the unit memory cell group.

摘要翻译： 根据实施例，半导体存储器包括字线，一组位线的多组，存储单元，写/读电路和字线选择电路。 在将程序数据的反相数据写入存储单元的状态下，施加应力，将程序数据编程到存储单元。 写入/读取电路将编程时的相同程序数据的反相数据写入由与存储单元连接的一组位线组成的单元存储单元组，并从单元存储单元组中读取数据 在读取时检测该位线对的信号电平。 字线选择电路同时选择并驱动连接到单元存储单元组的字线的两个或多个字线。

公开(公告)号：US20160035405A1

公开(公告)日：2016-02-04

申请号：US14638269

申请日：2015-03-04

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Atsushi KAWASUMI

IPC分类号： G11C11/16 ,  G11C11/417

CPC分类号： G11C11/1697 ,  G11C5/147 ,  G11C5/148 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693

摘要： According to one embodiment, a semiconductor device includes a first transistor of a first conductivity type, and a first logical circuit. The first transistor of the first conductivity type is connected between a first node to which a power supply voltage is applied and a second node. The first transistor is turned on in the initial stage of an active cycle, and is turned off by applying the power supply voltage to the second node. The first logical circuit is driven by the power supply voltage applied to the second node. The first logical circuit outputs a voltage which is lower than the power supply voltage in the active cycle based on an input signal supplied thereto.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一晶体管和第一逻辑电路。 第一导电类型的第一晶体管连接在施加电源电压的第一节点和第二节点之间。 第一晶体管在有效周期的初始阶段导通，并且通过将电源电压施加到第二节点而被关断。 第一逻辑电路由施加到第二节点的电源电压驱动。 第一逻辑电路基于提供给其的输入信号输出低于有效周期中的电源电压的电压。

公开(公告)号：US20170069659A1

公开(公告)日：2017-03-09

申请号：US15063115

申请日：2016-03-07

申请人： Kabushiki Kaisha Toshiba

发明人： Atsushi KAWASUMI

IPC分类号： H01L27/118

CPC分类号： H01L27/11807 ,  H01L27/1104 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11812 ,  H01L2027/11838 ,  H01L2027/11848 ,  H01L2027/11864 ,  H01L2027/11881

摘要： According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.

摘要翻译： 根据一个实施例，半导体存储器100包括由包括NMOS晶体管和PMOS晶体管的多个SRAM单元10组成的存储单元阵列100A，以及连接到存储单元阵列的接地GND1或电源电压VDD1的偏置电路100B 100A。 偏置电路100B包括在沟道长度和沟道宽度以及沟道部分的掺杂剂和剂量方面与SRAM单元10的NMOS晶体管相同的NMOS晶体管121,122,133和134以及PMOS晶体管 111和112在沟道长度和沟道宽度方面与SRAM单元10的PMOS晶体管相同，并且就沟道部分的掺杂剂和剂量而言是相同的。 NMOS晶体管和PMOS晶体管的扩散区域形成在相同的半导体层中。

公开(公告)号：US20140071745A1

公开(公告)日：2014-03-13

申请号：US14019865

申请日：2013-09-06

申请人： Kabushiki Kaisha Toshiba

发明人： Atsushi KAWASUMI

IPC分类号： G11C11/16

CPC分类号： G11C11/1673 ,  G11C5/147 ,  G11C7/062 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054

摘要： According to one embodiment, a magnetoresistive memory device includes first and second bit lines, a memory cell, a power supply line, first and second transistors, and third and fourth transistors. The memory cell has first and second magnetoresistive elements and is connected between the first and second bit lines. The power supply line is connected between the first and second magnetoresistive elements. The first and second transistors have current paths inserted in the first and second bit lines, respectively, and have gate electrodes connected, respectively to the second and first bit lines provided on a side opposite to the memory cell. The third and fourth transistors are inserted in the first and second bit lines. Gate electrodes of the third and fourth transistors are cross-coupled, and the third and fourth transistors are controlled by current from the memory cell.

摘要翻译： 根据一个实施例，磁阻存储器件包括第一和第二位线，存储单元，电源线，第一和第二晶体管以及第三和第四晶体管。 存储单元具有第一和第二磁阻元件，并连接在第一和第二位线之间。 电源线连接在第一和第二磁阻元件之间。 第一和第二晶体管分别具有插入在第一和第二位线中的电流路径，并且分别将栅电极连接到设置在与存储单元相对的一侧上的第二位线和第一位线。 第三和第四晶体管插入第一和第二位线。 第三和第四晶体管的栅极交叉耦合，并且第三和第四晶体管由来自存储单元的电流控制。