公开(公告)号：US10388793B2

公开(公告)日：2019-08-20

申请号：US15819486

申请日：2017-11-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC分类号： H01L29/78 ,  H01L29/66 ,  B29C48/21 ,  B29C48/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  B29C37/00 ,  B32B3/08 ,  B32B7/02 ,  B32B27/00 ,  B32B27/08 ,  B32B27/28 ,  B32B27/30 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  H01G4/005 ,  H01G4/14 ,  H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L27/088 ,  B29K23/00 ,  B29K105/16 ,  B29K507/04 ,  B29L9/00 ,  B29L31/34

摘要： A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

公开(公告)号：US10283374B2

公开(公告)日：2019-05-07

申请号：US14882549

申请日：2015-10-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Robert R. Robison

IPC分类号： H01L23/62 ,  H01L21/324 ,  H01L27/02 ,  H01L29/866 ,  H01L29/861

摘要： Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

公开(公告)号：US10090400B2

公开(公告)日：2018-10-02

申请号：US15441364

申请日：2017-02-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/265

摘要： A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

公开(公告)号：US09869708B2

公开(公告)日：2018-01-16

申请号：US14882756

申请日：2015-10-14

申请人： International Business Machines Corporation

发明人： Shunhua Chang ,  James Paul Di Sarro ,  Robert J. Gauthier, Jr. ,  Nathan Jack ,  Souvick Mitra

IPC分类号： H02H3/22 ,  G01R31/00 ,  H02H9/04 ,  G01R31/28 ,  H01L27/02 ,  H05K9/00

CPC分类号： G01R31/002 ,  G01R31/2851 ,  H01L27/0248 ,  H02H9/046 ,  H05K9/0067

摘要： A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.

公开(公告)号：US09397163B2

公开(公告)日：2016-07-19

申请号：US14882809

申请日：2015-10-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC分类号： H01L29/78 ,  H01L29/08

CPC分类号： H01L29/7856 ,  B29C37/0025 ,  B29C47/065 ,  B29C47/56 ,  B29K2023/12 ,  B29K2105/16 ,  B29K2507/04 ,  B29K2995/0005 ,  B29K2995/0007 ,  B29L2009/003 ,  B29L2009/005 ,  B29L2031/34 ,  B32B3/08 ,  B32B7/02 ,  B32B27/00 ,  B32B27/08 ,  B32B27/28 ,  B32B27/306 ,  B32B27/308 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B2262/106 ,  B32B2264/105 ,  B32B2264/12 ,  B32B2270/00 ,  B32B2274/00 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/206 ,  B32B2307/518 ,  B32B2307/732 ,  B32B2457/16 ,  H01G4/005 ,  H01G4/14 ,  H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7851 ,  H01L2029/7858

摘要： A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

摘要翻译： 公开了一种围绕翅片双扩散金属氧化物半导体（DMOS）的器件和制造方法。 该方法包括从衬底形成多个翅片结构。 该方法还包括在衬底内形成第一导电类型和第二导电类型的阱以及多个翅片结构中相应的翅片结构。 该方法还包括在第一鳍片结构的暴露部分上形成源极接触。 该方法还包括在相邻鳍片结构的暴露部分上形成到第一鳍片结构的漏极接触。 该方法还包括在介电填充材料周围形成围绕第一鳍结构并在第一导电类型的阱上延伸的栅极结构。

公开(公告)号：US09281379B1

公开(公告)日：2016-03-08

申请号：US14547780

申请日：2014-11-19

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC分类号： H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7856 ,  B29C37/0025 ,  B29C47/065 ,  B29C47/56 ,  B29K2023/12 ,  B29K2105/16 ,  B29K2507/04 ,  B29K2995/0005 ,  B29K2995/0007 ,  B29L2009/003 ,  B29L2009/005 ,  B29L2031/34 ,  B32B3/08 ,  B32B7/02 ,  B32B27/00 ,  B32B27/08 ,  B32B27/28 ,  B32B27/306 ,  B32B27/308 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B2262/106 ,  B32B2264/105 ,  B32B2264/12 ,  B32B2270/00 ,  B32B2274/00 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/206 ,  B32B2307/518 ,  B32B2307/732 ,  B32B2457/16 ,  H01G4/005 ,  H01G4/14 ,  H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7851 ,  H01L2029/7858

摘要： A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

公开(公告)号：US09070629B2

公开(公告)日：2015-06-30

申请号：US14054033

申请日：2013-10-15

申请人： International Business Machines Corporation

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L23/48 ,  H01L21/66 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L22/30 ,  H01L21/76886 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  Y10T29/5313 ,  Y10T29/532 ,  H01L2924/00

摘要： Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

摘要翻译： 用于改变布线路径的电阻的方法和系统。 将布线路径的电阻与目标电阻值进行比较。 如果布线路径的电阻超过目标电阻值，则选择性地向布线路径施加电流，以物理地改变布线路径的一部分。 可以选择电流来改变布线路径，使得电阻下降到小于或等于目标电阻值的值。

公开(公告)号：US09041127B2

公开(公告)日：2015-05-26

申请号：US13893466

申请日：2013-05-14

申请人： International Business Machines Corporation

发明人： John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC分类号： H01L29/76 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7816

摘要： The present invention is a finFET type semiconductor device using LDMOS features. The device includes a first portion of a substrate doped with a second doping type and has a first trench, second trench, and first fin. The second portion of the substrate with a first doping type includes a third trench and second fin. The second fin between the second and third trench covers a part the first portion and a part of the second portion of the substrate. A first segment of the second fin is between the second segment and second trench. A second segment covers a part of the second portion of the substrate and is between the first segment and third trench. A gate covering at least a part of the first segment and a part of the first portion and a part of the second portion of the substrate.

摘要翻译： 本发明是使用LDMOS特征的finFET型半导体器件。 该器件包括掺杂有第二掺杂类型的衬底的第一部分，并且具有第一沟槽，第二沟槽和第一鳍片。 具有第一掺杂类型的衬底的第二部分包括第三沟槽和第二鳍片。 第二和第三沟槽之间的第二鳍状物覆盖衬底的第一部分和第二部分的一部分。 第二鳍片的第一片段在第二片段和第二沟槽之间。 第二段覆盖衬底的第二部分的一部分并且在第一段和第三沟槽之间。 覆盖所述第一部分的至少一部分以及所述第一部分的一部分和所述基板的第二部分的一部分的栅极。

公开(公告)号：US08847354B2

公开(公告)日：2014-09-30

申请号：US13749146

申请日：2013-01-24

申请人： International Business Machines Corporation

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Anthony K. Stamper

IPC分类号： H01L21/02 ,  H01L29/94 ,  H01L23/522 ,  H01L49/02 ,  H01L27/02

CPC分类号： H01L28/82 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.

摘要翻译： 金属绝缘体金属（MIM）电容器和制造MIM电容器的方法。 MIM电容器包括层间绝缘层（ILD）层，其中各孔由多个侧壁限定，并且各自从ILD层的顶表面延伸到第一层间电介质层。 布置在孔的侧壁和ILD层的顶表面上的层叠层包括底部导电电极，顶部导电电极和位于底部和顶部导电电极之间的电容器电介质。

公开(公告)号：US20140264752A1

公开(公告)日：2014-09-18

申请号：US13828936

申请日：2013-03-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L49/02

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments include dual three-dimensional (3D) resistor structures and methods of forming such structures. In some embodiments, a dual 3D resistor structure includes: a dielectric layer having a first set of trenches extending in a first direction through the dielectric layer; and a second set of trenches overlayed on the first set of trenches, the second set of trenches extending in a second direction through the dielectric layer, the second set of trenches and the first set of trenches forming at least one dual 3D trench; and a resistor material overlying the dielectric layer and at least partially filling the at least one dual 3D trench along the first direction and the second direction.

摘要翻译： 各种实施例包括双重三维（3D）电阻器结构和形成这种结构的方法。 在一些实施例中，双3D电阻器结构包括：电介质层，具有沿第一方向延伸穿过电介质层的第一组沟槽; 以及覆盖在所述第一组沟槽上的第二组沟槽，所述第二组沟槽沿第二方向延伸穿过所述介电层，所述第二组沟槽和所述第一组沟槽形成至少一个双3D沟槽; 以及覆盖所述电介质层并且沿着所述第一方向和所述第二方向至少部分地填充所述至少一个双3D沟槽的电阻器材料。