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    System and method for a single stage tunable ultra-wideband pulse generator
    1.
    发明授权
    System and method for a single stage tunable ultra-wideband pulse generator 有权
    单级可调谐超宽带脉冲发生器的系统和方法

    公开(公告)号：US07869526B2

    公开(公告)日：2011-01-11

    申请号：US11612713

    申请日：2006-12-19

    Applicant: Erick Maxwell ,  Thomas Weller

    Inventor： Erick Maxwell ,  Thomas Weller

    IPC: H04L27/00

    CPC classification number: H03K5/12 ,  H03K3/33 ,  H03K5/06 ,  H04B1/7174

    Abstract: The present invention provides a single-stage tunable Ultra-Wideband (UWB) pulse generator, by creating and differentiating a variable edge rate signal. Edge rate variability is introduced by first applying a step recovery diode (SRD) to compress the edges of the source and then applying a simple RC network to adjust the edge rate. Next, the resulting signal is differentiated using microstrip transmission lines. The tunable generator resulting from this approach demonstrates a Gaussian and monocycle pulses with good symmetry and low distortion over the tunable range.

    Abstract translation: 本发明通过创建和区分可变边缘速率信号来提供单级可调谐超宽带（UWB）脉冲发生器。 通过首先应用步骤恢复二极管（SRD）来压缩源的边缘，然后应用简单的RC网络来调整边缘速率来引入边缘率变化。 接下来，使用微带传输线对结果信号进行区分。 由该方法产生的可调谐发生器表现出在可调范围内具有良好对称性和低失真的高斯和单周期脉冲。

    Narrow ultra wideband pulse generator
    2.
    发明申请
    Narrow ultra wideband pulse generator 有权
    窄超宽带脉冲发生器

    公开(公告)号：US20060267652A1

    公开(公告)日：2006-11-30

    申请号：US11167599

    申请日：2005-06-28

    Applicant: Moti Kabelly ,  Yossi Keren

    Inventor： Moti Kabelly ,  Yossi Keren

    IPC: H03K5/04

    CPC classification number: H03K3/33

    Abstract: A circuitry for generating a narrow impulse including an input device coupled to a matching circuitry that is coupled to a step recovery diode (SRD). The input device is configured to receive a succession of digital input signals, each characterized by having high level and low level portions. The signals having less than 50% duty cycle. The input device is configured to drive forward the SRD through the matching circuitry during the high level portion of the digital signal, whereby the SRD stores sufficient power for generating the narrow impulse following the falling edge of the high level portion of the digital input signal.

    Abstract translation: 一种用于产生窄脉冲的电路，包括耦合到耦合到阶跃恢复二极管（SRD）的匹配电路的输入装置。 输入设备被配置为接收一系列数字输入信号，每个特征在于具有高电平和低电平部分。 信号占空比小于50％。 输入装置被配置为在数字信号的高电平部分期间通过匹配电路驱动SRD，由此SRD存储足够的功率用于在数字输入信号的高电平部分的下降沿之后产生窄脉冲。

    Low power dual sampler utilizing step recovery diodes (SRDS)
    3.
    发明授权
    Low power dual sampler utilizing step recovery diodes (SRDS) 失效
    低功率双采样器利用步进恢复二极管（SRDS）

    公开(公告)号：US5708377A

    公开(公告)日：1998-01-13

    申请号：US606380

    申请日：1996-02-23

    Applicant: Donald A. Bradley

    Inventor： Donald A. Bradley

    IPC: H03D3/28 ,  H03D9/06 ,  H03K3/33 ,  G11C27/02

    CPC classification number: H03K3/33 ,  H03D9/0608 ,  H03D3/28

    Abstract: A low power dual sampler including two sampler switches with a step recovery diode (SRD) in each sampler switch. A local oscillator (LO) signal is provided through a power amplifier and transformer to baluns in the sampler switches without utilizing a power splitter, providing limited power loss to each balun. Each balun is configured to provide the LO signal to terminals of the SRD in a sampler switch without providing a termination to SRD impulses. Each sampler switch further includes series diodes connected across the terminals of each SRD switch with a junction of the series diodes connected to receive an RF signal, and the terminals of each SRD connected for providing an IF signal. To limit phase shift between SRD impulses, a temperature compensation circuit provides a DC offset voltage to each SRD. In one embodiment, each temperature compensation circuit includes an operational amplifier having a noninverting terminal coupled to a terminal of an SRD, an inverting terminal connected by a first resistor to ground, and an output connected by a second resistor to the inverting terminal and by a third resistor to the non-inverting terminal. To provide isolation between the sampler switches, a capacitor providing a high impedance to the LO signal and a low impedance to RF signals is connected at the interconnection of the sampler switches.

    Abstract translation: 一个低功率双采样器，包括两个采样器开关，每个采样器开关带有一个阶跃恢复二极管（SRD）。 通过功率放大器和变压器将本地振荡器（LO）信号提供给采样器开关中的巴伦，而不使用功率分配器，为每个平衡 - 不平衡变压器提供有限的功率损耗。 每个平衡 - 不平衡转换器被配置为向采样器开关中的SRD的端子提供LO信号，而不向SRD脉冲提供终止。 每个采样器开关还包括连接在每个SRD开关的端子之间的串联二极管，其中串联二极管的接点连接以接收RF信号，并且每个SRD的端子用于提供IF信号。 为了限制SRD脉冲之间的相移，温度补偿电路为每个SRD提供DC偏移电压。 在一个实施例中，每个温度补偿电路包括运算放大器，其具有耦合到SRD的端子的非反相端子，由第一电阻器接地连接的反相端子以及由第二电阻器连接到反相端子的输出端以及由 第三个电阻到同相端子。 为了在采样器开关之间提供隔离，在采样器开关的互连处连接向LO信号提供高阻抗的电容器和RF信号的低阻抗。

    Pulse shaping circuit
    5.
    发明授权
    Pulse shaping circuit 失效

    公开(公告)号：US3622808A

    公开(公告)日：1971-11-23

    申请号：US3622808D

    申请日：1969-09-15

    Applicant: IWATSU ELECTRIC CO LTD

    Inventor： UCHIDA KOZO

    IPC: H03K3/33 ,  H03K17/00

    CPC classification number: H03K3/33

    Abstract: A pulse shaping circuit for producing high-frequency pulses of extremely steep waveform is comprised by a first snap-off diode connected between input and output terminals, a second snap-off diode connected to the juncture between the first snap-off diode and the output terminal and an impedance connected between the ground and the juncture between the input terminal and the first snap-off diode, the first and second snap-off diodes being poled oppositely with respect to the output terminal. The width of the shaped pulses is determined by the setting of the impedance. Sources of DC supply of suitable polarities may be connected to said impedance and said second snap-off diode.

    Circuit to control the duration of pulses
    6.
    发明授权
    Circuit to control the duration of pulses 失效
    电路控制脉冲的持续时间

    公开(公告)号：US3586884A

    公开(公告)日：1971-06-22

    申请号：US3586884D

    申请日：1968-12-23

    Applicant: INT STANDARD ELECTRIC CORP

    Inventor： GASSMANN GERHARD GUNTER

    IPC: H03K3/33 ,  H03K5/05 ,  H03K7/08 ,  H03K19/12 ,  H03K1/18

    CPC classification number: H03K5/05 ,  H03K3/33 ,  H03K7/08 ,  H03K19/12

    Abstract: The duration of pulses may be controlled to have a given constant width, or a variable width to convey intelligence by the circuit of this invention. A semiconductor device receives a pulse input whose width is to be maintained constant or varied. A bias voltage, constant or variable, is coupled to the control electrode of said device to adjust the storage time thereof. The output of said device and the pulse input are coupled to an OR gate to produce either said constant or variable width pulse output. Negative feedback to the control electrode may be employed to compensate the pulse output for temperature variations.

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