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公开(公告)号：US07750747B2
公开(公告)日：2010-07-06
申请号：US11905223
申请日：2007-09-28
申请人： Masazumi Marutani
发明人： Masazumi Marutani
IPC分类号： H03L7/085
摘要： A clock selection circuit and synthesizer that is capable of selecting an optimum clock signal from among a plurality of clock signals in a short time. A reference-clock counter counts clock pulses in an inputted reference clock signal (REF). A clock counter counts clock pulses in one of the plurality of clock signals which is selected by a selection unit and frequency-divided by a frequency divider. An instruction-signal output unit outputs a plurality of comparison-instruction signals during an interval in which a difference occurs between the counts of two of the plurality of clock signals having the closest frequencies. A comparison unit compares the count of the reference-clock counter and the count of the clock counter. The selection unit selects a clock signal by a binary search according to the result of the comparison.
摘要翻译： 一种时钟选择电路和合成器，其能够在短时间内从多个时钟信号中选择最佳时钟信号。 参考时钟计数器对输入的参考时钟信号（REF）中的时钟脉冲进行计数。 时钟计数器对由选择单元选择并被分频器分频的多个时钟信号之一计数时钟脉冲。 指令信号输出单元在具有最接近频率的多个时钟信号中的两个的计数之间发生差异的间隔期间输出多个比较指令信号。 比较单元比较参考时钟计数器的计数和时钟计数器的计数。 选择单元根据比较结果通过二进制搜索来选择时钟信号。
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公开(公告)号：US20080042760A1
公开(公告)日：2008-02-21
申请号：US11905223
申请日：2007-09-28
申请人： Masazumi Marutani
发明人： Masazumi Marutani
IPC分类号： H03B5/12
摘要： A clock selection circuit and synthesizer that is capable of selecting an optimum clock signal from among a plurality of clock signals in a short time. A reference-clock counter counts clock pulses in an inputted reference clock signal (REF). A clock counter counts clock pulses in one of the plurality of clock signals which is selected by a selection unit and frequency-divided by a frequency divider. An instruction-signal output unit outputs a plurality of comparison-instruction signals during an interval in which a difference occurs between the counts of two of the plurality of clock signals having the closest frequencies. A comparison unit compares the count of the reference-clock counter and the count of the clock counter. The selection unit selects a clock signal by a binary search according to the result of the comparison.
摘要翻译： 一种时钟选择电路和合成器，其能够在短时间内从多个时钟信号中选择最佳时钟信号。 参考时钟计数器对输入的参考时钟信号（REF）中的时钟脉冲进行计数。 时钟计数器对由选择单元选择并被分频器分频的多个时钟信号之一计数时钟脉冲。 指令信号输出单元在具有最接近的频率的多个时钟信号中的两个的计数之间发生差异的间隔期间输出多个比较指令信号。 比较单元比较参考时钟计数器的计数和时钟计数器的计数。 选择单元根据比较结果通过二进制搜索来选择时钟信号。
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3.发明授权Phase-locked loop circuit with switchable outputs for multiple loop filters 失效锁相环电路，具有多路环路滤波器的可切换输出
公开(公告)号：US6112068A
公开(公告)日：2000-08-29
申请号：US996008
申请日：1997-12-22
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/141
摘要： An electronic system, such as a wireless telephone handset (10), having multiple voltage-controlled oscillators (26, 28) so that the system can operate in a selected one of multiple frequency bands, is disclosed. Each of the voltage-controlled oscillators (26, 28) is associated with one of multiple loop filters (32, 34), which filter the control voltage (CP1, CP2) responsive to which the frequency of oscillation of the voltage-controlled oscillators (26, 28) controlled. Only one of the voltage-controlled oscillators (26, 28) is enabled at any one time, responsive to a control signal (VCOSEL). Synthesizer circuitry (30) includes a phase detector (44) which is coupled to a common node (VCOCLK) at which outputs of the voltage-controlled oscillators (26, 28) are coupled; the phase detector (44) compares the phase of this signal (VCODIV) to a reference signal (REFDIV) based on a reference clock (REFCLK), and controls a charge pump (46) accordingly. A switch (48) is provided to selectably apply the output of the charge pump (46) to the loop filter (32, 34) associated with the selected voltage-controlled oscillator (26, 28).
摘要翻译： 公开了一种诸如无线电话手机（10）的电子系统，其具有多个压控振荡器（26,28），使得系统可以在多个频带中选定的一个频带中工作。 每个压控振荡器（26,28）与多个环路滤波器（32,34）中的一个相关联，多个环路滤波器（32,34）对控制电压（CP1，CP2）进行滤波，响应于此，电压控制振荡器 26,28）控制。 响应于控制信号（VCOSEL），任何一个时间只使能一个压控振荡器（26,28）。 合成器电路（30）包括相位检测器（44），其耦合到公共节点（VCOCLK），在所述公共节点（VCOCLK）处耦合所述压控振荡器（26,28）的输出; 相位检测器（44）基于参考时钟（REFCLK）将该信号（VCODIV）的相位与参考信号（REFDIV）进行比较，并且相应地控制电荷泵（46）。 提供开关（48）以可选地将电荷泵（46）的输出施加到与所选择的压控振荡器（26,28）相关联的环路滤波器（32,34）。
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公开(公告)号：US4317228A
公开(公告)日：1982-02-23
申请号：US84707
申请日：1979-10-15
摘要： A television receiver includes a frequency synthesizer phase lock loop operated in a time multiplexed manner to provide two tuning signals for tuning a received television signal. The two tuning signals are developed at the outputs of first and second voltage controlled local oscillators alternately operated in response to a phase detector which is reset at the beginning of each alternate operation.
摘要翻译： 电视接收机包括以时间复用方式操作的频率合成器锁相环，以提供用于调谐所接收的电视信号的两个调谐信号。 两个调谐信号在第一和第二电压控制的本地振荡器的输出处被开发，该第一和第二电压控制的本地振荡器响应于在每个替换操作开始时复位的相位检测器交替地操作。
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公开(公告)号：US20240204787A1
公开(公告)日：2024-06-20
申请号：US18431019
申请日：2024-02-02
发明人： Brent CARLSON
CPC分类号： H03L7/0991 , H03L7/141 , H03L7/24
摘要： A method for timing aperture synthesis arrays comprising the steps of: (a) coupling a plurality of independent crystal oscillators, each of the plurality of independent crystal oscillators having a unique output frequency; (b) digitally synchronizing the plurality of independent crystal oscillators in phase; (c) combining the unique output frequencies; and (d) obtaining a stable digital reference signal for timing at least one remote radio device of the aperture synthesis array.
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6.发明申请公开(公告)号：US20110134964A1
公开(公告)日：2011-06-09
申请号：US13059460
申请日：2009-08-12
摘要： A frequency generating arrangement for generation of at least two predetermined frequencies is introduced. The arrangement comprises a phase locked loop circuit with at least two control value storage units and at least one controlled oscillator unit, wherein the control value storage units being configured to selectively output a control signal to the at least one voltage controlled oscillator unit, causing generation of one of the at least two predetermined frequencies. Frequency generating system for generation of ultra-fast hopping-frequency sequences comprises at least a first and a second frequency generating arrangement and further a controlling unit and a multiplexer unit for selectively connecting only one of the outputs of the two frequency generating arrangements with an output of the system. The controlling unit can be configured to control the system to generate a predetermined frequency sequence by controlling the two frequency generating arrangements such that during the period, in which one of the frequency generating arrangements is connected with the output of the system, the other frequency generating arrangement is controlled to lock to a next predetermined frequency of the predetermined frequency sequence, and to control the multiplexer unit pass the output of the other frequency generating arrangement to the system output after a predetermined time period; and repeating the controlling step in order to generate the predetermined frequency sequence.
摘要翻译： 引入用于产生至少两个预定频率的频率产生装置。 该装置包括具有至少两个控制值存储单元和至少一个受控振荡器单元的锁相环电路，其中控制值存储单元被配置为选择性地向至少一个压控振荡器单元输出控制信号， 所述至少两个预定频率中的一个。 用于产生超快跳频序列的频率产生系统至少包括第一和第二频率产生装置，还包括控制单元和多路复用器单元，用于选择性地将两个频率发生装置的输出之一与输出 的系统。 控制单元可以被配置为通过控制两个频率产生装置来控制系统以产生预定的频率序列，使得在频率产生装置中的一个与系统的输出连接的时间段内产生另一个频率 控制装置锁定到预定频率序列的下一个预定频率，并且在预定时间段之后控制多路复用器单元将另一频率产生装置的输出传递给系统输出; 并重复所述控制步骤以产生所述预定频率序列。
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公开(公告)号：US5781847A
公开(公告)日：1998-07-14
申请号：US526025
申请日：1995-09-08
申请人： Ian M. Clarke , Stuart M. Feeney
发明人： Ian M. Clarke , Stuart M. Feeney
摘要： In multiple-channel microwave transmitters and communications systems, such as multi-point video distribution systems operating at frequencies of around 29 GHz or 40 GHz, good frequency stability for each of the channel frequencies is achieved with a feed-back loop including an error detector circuit. The error detector circuit (39,29) is coupled between a sampler and an input circuit of the source. This detector circuit detects any drift or other error in the carrier frequency of the sample from the desired microwave frequency for that channel signal and provides a corrective signal to the input circuit. The part of the feed-back loop comprising at least a part of the detector circuit is common to a group of the channels. Switch means couple the common part of the feed-back loop between the sampler and the source input circuit of each channel, and so permit this common part to be time multiplexed between the respective feed-back loops of the group of channels. The input circuit for each source applies an up-datable bias signal for regulating the frequency of the source in accordance with the last corrective signal generated by the detector circuit for that source. By adopting such a stabilisation arrangement in accordance with the present invention, expensive component parts of the feed-back loop can be common to a group of the channels, so reducing the assembly cost of the multiple-channel transmitter. Good long-term frequency stability for all the channels can be obtained, including a reliably constant frequency relationship between the channels.
摘要翻译： 在多通道微波发射器和通信系统中，例如在大约29GHz或40GHz的频率下操作的多点视频分配系统，通过包括误差检测器的反馈回路来实现每个通道频率的良好的频率稳定性 电路。 误差检测器电路（39,29）耦合在采样器和源的输入电路之间。 该检测器电路从该通道信号的期望的微波频率检测样品的载波频率中的任何漂移或其他误差，并向输入电路提供校正信号。 包括检测器电路的至少一部分的反馈回路的部分对于一组通道是共同的。 开关意味着将每个通道的采样器和源输入电路之间的反馈回路的公共部分耦合，因此允许这个公共部分在通道组的各个反馈回路之间进行时间复用。 每个源的输入电路根据由该源的检测器电路产生的最后一个校正信号施加可调节偏置信号，用于调节源的频率。 通过采用根据本发明的这种稳定装置，反馈回路的昂贵组件可以是一组通道共同的，因此降低了多通道发射机的组装成本。 可以获得所有通道的良好的长期频率稳定性，包括通道之间可靠恒定的频率关系。
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8.发明授权
公开(公告)号：US4629999A
公开(公告)日：1986-12-16
申请号：US565956
申请日：1983-12-27
申请人： Douglas J. Hatch , Jeffrey L. Cox
发明人： Douglas J. Hatch , Jeffrey L. Cox
摘要： A phase-locked loop capable of generating a plurality of stable frequncy signals. This loop includes a plurality of voltage controlled oscillators which are sequentially coupled to the output of a phase sensitive detector by a multiplexer. RF switches then sequentially couple, in synchronism with the multiplexer, the oscillator outputs to a programmable divider which, in turn, is coupled to an input of the phase sensitive detector, the other input thereto being coupled to a reference oscillator. The dividing factors for the programmable divider are inputted thereto, in synchronism with the multiplexer, from a memory.
摘要翻译： 一种能产生多个稳定频率信号的锁相环。 该回路包括多个压控振荡器，其通过多路复用器顺序地耦合到相敏检测器的输出端。 然后，RF开关与多路复用器同步地顺序地将振荡器输出耦合到可编程分频器，该可编程分频器又耦合到相敏检测器的输入，其另一个输入耦合到参考振荡器。 可编程分频器的分频因子与多路复用器同步地从存储器输入到其中。
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公开(公告)号：US4259744A
公开(公告)日：1981-03-31
申请号：US70204
申请日：1979-08-27
申请人： Michael T. Junod , Albert M. Bates
发明人： Michael T. Junod , Albert M. Bates
摘要： A simultaneous multichannel signal generator incorporating phase-locked l frequency correction. For each channel, there is a voltage-controlled oscillator (VCO) set to an appropriate frequency by a tuning signal and modulated by a channel data signal. The output signals from all VCO's are provided to a summer and then are appropriately amplified and filtered for transmission. A single multiplexed frequency correction circuit compares the phase of a reference frequency signal with the phase of a VCO output signal whose frequency has been divided, by a divide-by-N counter, to the reference frequency. If the divided VCO signal is out of phase with the reference frequency signal, an appropriate correction signal is provided to the device providing voltage control for that VCO.
摘要翻译： 并入多通道信号发生器并入锁相环频率校正。 对于每个通道，通过调谐信号将压控振荡器（VCO）设置为适当的频率并由通道数据信号调制。 来自所有VCO的输出信号被提供给一个加法器，然后被适当地放大和滤波以便传输。 单个多路复用频率校正电路将参考频率信号的相位与频率已被除以N计数器的VCO输出信号的相位与参考频率进行比较。 如果分频VCO信号与参考频率信号异相，则向提供该VCO的电压控制的器件提供适当的校正信号。
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公开(公告)号：US20240171183A1
公开(公告)日：2024-05-23
申请号：US18430958
申请日：2024-02-02
发明人： Brent CARLSON
CPC分类号： H03L7/0991 , H03L7/141 , H03L7/24
摘要： A method for timing aperture synthesis arrays comprising the steps of: (a) coupling a plurality of independent crystal oscillators, each of the plurality of independent crystal oscillators having a unique output frequency; (b) digitally synchronizing the plurality of independent crystal oscillators in phase; (c) combining the unique output frequencies; and (d) obtaining a stable digital reference signal for timing at least one remote radio device of the aperture synthesis array.
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