公开(公告)号：US09923574B2

公开(公告)日：2018-03-20

申请号：US15663411

申请日：2017-07-28

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Emmanuel Philippe Christian Hardy

IPC: H03M7/30 ,  H03M1/18 ,  H03M1/50 ,  H03M3/00 ,  H03K7/08 ,  H03K9/08

CPC classification number: H03M7/30 ,  H03K7/08 ,  H03K9/08 ,  H03M1/18 ,  H03M1/181 ,  H03M1/50 ,  H03M1/504 ,  H03M3/484 ,  H03M2201/00

Abstract: This application relates to analog-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analog input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

公开(公告)号：US20160359500A1

公开(公告)日：2016-12-08

申请号：US15243305

申请日：2016-08-22

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul LESSO ,  Emmanuel Philippe Christian HARDY

IPC: H03M7/30

CPC classification number: H03M7/30 ,  H03K7/08 ,  H03K9/08 ,  H03M1/18 ,  H03M1/181 ,  H03M1/50 ,  H03M1/504 ,  H03M3/484 ,  H03M2201/00

Abstract: This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

公开(公告)号：US09748971B2

公开(公告)日：2017-08-29

申请号：US15243305

申请日：2016-08-22

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Emmanuel Philippe Christian Hardy

IPC: H03M7/30 ,  H03M1/18 ,  H03M1/50 ,  H03M3/00 ,  H03K7/08 ,  H03K9/08

CPC classification number: H03M7/30 ,  H03K7/08 ,  H03K9/08 ,  H03M1/18 ,  H03M1/181 ,  H03M1/50 ,  H03M1/504 ,  H03M3/484 ,  H03M2201/00

Abstract: This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

公开(公告)号：US09425813B2

公开(公告)日：2016-08-23

申请号：US14931332

申请日：2015-11-03

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Emmanuel Philippe Christian Hardy

IPC: H03M1/18 ,  H03M1/50 ,  H03M3/00

CPC classification number: H03M7/30 ,  H03K7/08 ,  H03K9/08 ,  H03M1/18 ,  H03M1/181 ,  H03M1/50 ,  H03M1/504 ,  H03M3/484 ,  H03M2201/00

Abstract: This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

Abstract translation: 本申请涉及模拟 - 数字转换器（ADC）。 ADC200具有第一转换器（201），用于接收模拟输入信号（AIN），并输出诸如脉冲宽度调制（PWM）信号的时间编码信号（DT），其基于输入信号和第一转换 增益设置（GIN）。 在一些实施例中，第一转换器具有用于产生PWM信号的PWM调制器（401），使得输入信号由可在时间上连续变化的脉冲宽度编码。 第二转换器（202）接收时间编码信号并基于时间编码信号（DT）和第二转换增益设置（GO）输出数字输出信号（DOUT）。 第二转换器可以具有第一PWM到数字调制器（403）。 增益分配块（204）基于时间编码信号（DT）生成第一和第二转换增益设置。 增益分配块（204）可以具有第二PWM到数字调制器（203），其可以具有第一PWM到数字调制器（403）的较低等待时间和/或更低的分辨率。

公开(公告)号：US20170346501A1

公开(公告)日：2017-11-30

申请号：US15663411

申请日：2017-07-28

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul LESSO ,  Emmanuel Philippe Christian HARDY

IPC: H03M7/30 ,  H03M1/50 ,  H03M1/18 ,  H03M3/00 ,  H03K9/08 ,  H03K7/08

CPC classification number: H03M7/30 ,  H03K7/08 ,  H03K9/08 ,  H03M1/18 ,  H03M1/181 ,  H03M1/50 ,  H03M1/504 ,  H03M3/484 ,  H03M2201/00

Abstract: This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

公开(公告)号：US20160126968A1

公开(公告)日：2016-05-05

申请号：US14931332

申请日：2015-11-03

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Emmanuel Philippe Christian Hardy

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/38 ,  H03M1/00

CPC classification number: H03M7/30 ,  H03K7/08 ,  H03K9/08 ,  H03M1/18 ,  H03M1/181 ,  H03M1/50 ,  H03M1/504 ,  H03M3/484 ,  H03M2201/00

Abstract: This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

Abstract translation: 本申请涉及模拟 - 数字转换器（ADC）。 ADC200具有第一转换器（201），用于接收模拟输入信号（AIN），并输出诸如脉冲宽度调制（PWM）信号的时间编码信号（DT），其基于输入信号和第一转换 增益设置（GIN）。 在一些实施例中，第一转换器具有用于产生PWM信号的PWM调制器（401），使得输入信号由可在时间上连续变化的脉冲宽度编码。 第二转换器（202）接收时间编码信号并基于时间编码信号（DT）和第二转换增益设置（GO）输出数字输出信号（DOUT）。 第二转换器可以具有第一PWM到数字调制器（403）。 增益分配块（204）基于时间编码信号（DT）生成第一和第二转换增益设置。 增益分配块（204）可以具有第二PWM到数字调制器（203），其可以具有第一PWM到数字调制器（403）的较低等待时间和/或更低的分辨率。