公开(公告)号：US20050060595A1

公开(公告)日：2005-03-17

申请号：US10663098

申请日：2003-09-15

申请人： Tsvika Kurts ,  John Horigan

发明人： Tsvika Kurts ,  John Horigan

IPC分类号： G06F1/04 ,  G06F21/00 ,  H03K5/19

CPC分类号： H03K5/19 ,  G06F21/71 ,  G06F21/725

摘要： A processor provides a configured clock rate setting for use by a peripheral set. The processor receives back from the peripheral set a feedback clock rate setting. The configured clock rate setting and the feedback clock rate setting are compared to detect over-clocking of the processor.

摘要翻译： 处理器提供配置的时钟速率设置供外设使用。 处理器从外围设备接收反馈时钟速率设置。 将配置的时钟速率设置和反馈时钟速率设置进行比较，以检测处理器的超频。

公开(公告)号：US20060184812A1

公开(公告)日：2006-08-17

申请号：US11402527

申请日：2006-04-11

申请人： Don Nguyen ,  Pochang Hsu ,  Robert Jackson ,  John Horigan

发明人： Don Nguyen ,  Pochang Hsu ,  Robert Jackson ,  John Horigan

IPC分类号： G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

公开(公告)号：US20050139345A1

公开(公告)日：2005-06-30

申请号：US10750722

申请日：2003-12-31

申请人： Himanshu Pokharna ,  Rajiv Mongia ,  Ravi Prasher ,  Sridhar Machiroutu ,  Je-Young Chang ,  John Horigan

发明人： Himanshu Pokharna ,  Rajiv Mongia ,  Ravi Prasher ,  Sridhar Machiroutu ,  Je-Young Chang ,  John Horigan

IPC分类号： F28F7/00 ,  H01L23/427 ,  H01L23/473 ,  H02K44/04 ,  H05K7/20

CPC分类号： H02K44/04 ,  F28D15/00 ,  F28F23/00 ,  H01L23/427 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus for using fluid laden with nanoparticles for application in electronic cooling is described. In one embodiment, an electromagnetic pump is used to circulate the nanoparticle laden fluid.

摘要翻译： 描述了一种使用载有纳米颗粒的液体用于电子冷却的装置。 在一个实施例中，使用电磁泵来循环载有纳米颗粒的流体。

公开(公告)号：US20070239922A1

公开(公告)日：2007-10-11

申请号：US11299103

申请日：2005-12-09

申请人： John Horigan

发明人： John Horigan

IPC分类号： G06F13/40 ,  G06F13/38

CPC分类号： G06F13/4286 ,  Y02D10/14 ,  Y02D10/151

摘要： A technique to reconfigure a link within a common system interface (CSI) link. More particularly, embodiments described herein relate to transmitting a signal to reconfigure a link while data is concurrently allowed to be transmitted across the link.

摘要翻译： 在公共系统接口（CSI）链路中重新配置链路的技术。 更具体地，这里描述的实施例涉及发送信号以重新配置链路，同时允许跨链路传输数据。

公开(公告)号：US20060137377A1

公开(公告)日：2006-06-29

申请号：US11027433

申请日：2004-12-29

申请人： Eric Samson ,  John Horigan ,  Robert Jackson ,  Shreekant Thakkar

发明人： Eric Samson ,  John Horigan ,  Robert Jackson ,  Shreekant Thakkar

IPC分类号： F25B41/00 ,  F25D23/12 ,  F15B7/00

CPC分类号： G06F1/206

摘要： A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component or the master component may be a central processing unit, a graphics memory and controller hub, or a central processing unit memory controller hub. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy. The selection policy may be received from a user through a graphical user interface. The selection policy may be based on an action being performed by the computing system.

摘要翻译： 公开了一种用于节流计算机系统的从属组件以在接收到第一信号时降低计算系统的总体温度的系统和方法。 第一信号可以来自主组件，指示主组件的温度已经超过其阈值温度。 从属组件或主组件可以是中央处理单元，图形存储器和控制器集线器，或中央处理单元存储器控制器集线器。 从组件可以发送第二信号以指示从组件的温度已超过其温度。 然后，主组件将启动主组件的节流以降低计算系统的整体温度。 主部件可以被节流到比从属部件小的程度。 可以将第一组件指定为主组件，并且可以基于选择策略将第二组件指定为从组件。 可以通过图形用户界面从用户接收选择策略。 选择策略可以基于由计算系统执行的动作。

公开(公告)号：US20060095806A1

公开(公告)日：2006-05-04

申请号：US11300716

申请日：2005-12-13

申请人： Xia Dai ,  John Horigan ,  Millind Mittal ,  Leslie Cline

发明人： Xia Dai ,  John Horigan ,  Millind Mittal ,  Leslie Cline

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F12/0891

摘要： In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

摘要翻译： 根据本发明的实施例，启动触发事件以将处理器置于低功率状态。 根据电源状态信号，处理器可能进入或不进入低功率状态时刷新高速缓存。 功率状态信号可以指示与将低处理器置于低功率状态相关联的功率降低的相对优先级，而无需首先刷新高速缓存，而与高功率状态中的电压降低相关联的高速缓存中的软错误率的增加。

公开(公告)号：US6014751A

公开(公告)日：2000-01-11

申请号：US841858

申请日：1997-05-05

申请人： James P. Kardach ,  John Horigan ,  Ravi Eakambaram ,  Tosaku Nakanishi ,  Chih-Hung Chung ,  Borys S. Senyk

发明人： James P. Kardach ,  John Horigan ,  Ravi Eakambaram ,  Tosaku Nakanishi ,  Chih-Hung Chung ,  Borys S. Senyk

IPC分类号： G06F1/04 ,  G06F1/32 ,  G06F12/08 ,  G06F1/10

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F12/0835 ,  Y02B60/1217 ,  Y02B60/1221

摘要： A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.

摘要翻译： 描述用于操作集成在降低功耗状态的方法和装置。 该装置包括功率降低逻辑，为了将集成电路置于降低功耗状态，将集成电路中的第一组和第二组功能单元的时钟信号置于门限。 第一组功能单元的特征在于需要在集成电路内执行高速缓存一致性操作。 该装置包括输入，该输入被耦合以通过集成电路外部的另外的设备将指示存储器访问的信号接收到由集成电路可访问的存储器资源。 响应于该信号的断言，功率降低逻辑将时钟信号传播到第一组功能单元，以使得该组功能单元能够执行高速缓存一致性操作，这可能由外部存储器访问所必需 设备。

公开(公告)号：US20070143514A1

公开(公告)日：2007-06-21

申请号：US11704760

申请日：2007-02-09

申请人： Shivnandan Kaushik ,  John Horigan ,  Alon Naveh ,  James Crossland

发明人： Shivnandan Kaushik ,  John Horigan ,  Alon Naveh ,  James Crossland

IPC分类号： G06F13/24 ,  G06F1/00

CPC分类号： G06F9/3851 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/329 ,  G06F9/4812 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/22 ,  Y02D10/24

摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.

摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。