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    Dual layer etch stop barrier
    1.
    发明授权
    Dual layer etch stop barrier 失效

    公开(公告)号：US06548418B2

    公开(公告)日：2003-04-15

    申请号：US10158249

    申请日：2002-05-30

    申请人： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

    发明人： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

    IPC分类号： H01L21302

    CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3185 ,  Y10S438/97

    摘要： A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.

    Dual layer etch stop barrier
    2.
    发明授权
    Dual layer etch stop barrier 失效
    双层蚀刻停止屏障

    公开(公告)号：US06420777B2

    公开(公告)日：2002-07-16

    申请号：US09031251

    申请日：1998-02-26

    申请人： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

    发明人： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

    IPC分类号： H01L2358

    CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3185 ,  Y10S438/97

    摘要： A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.

    摘要翻译： 提供了用于SiO 2的反应离子蚀刻的方法和用于这种蚀刻中的蚀刻阻挡层。 具有小于约0.8且优选化学计量量为0.75的六至奈比（x：y）的氮化硅（SixNy）阻挡层对正移动离子污染提供优异的回弹性，但蚀刻选择性差。 然而，六至氮（x：y）的比例为1.0或更大的氮化硅阻挡层相对于SiO 2具有优异的蚀刻选择性，但对于移动离子污染的正面阻挡性差。 在掺杂硅衬底上形成氮化硅屏障，该阻挡层具有两个部分。 一个部分相对于二氧化硅具有比第二部分更大的蚀刻选择性，并且第二部分比第一部分具有更大的对正性可移动离子透射的抵抗力。 与硅衬底相邻的一个部分的硅氮比小于约0.8。 在第一部分顶部形成的第二部分形成硅与氮的比大于约0.8。 优选地，两个部分一起为约50至约100纳米厚。

    Dual layer etch stop barrier
    3.
    发明授权
    Dual layer etch stop barrier 有权
    双层蚀刻停止屏障

    公开(公告)号：US06680259B2

    公开(公告)日：2004-01-20

    申请号：US10413087

    申请日：2003-04-14

    申请人： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

    发明人： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

    IPC分类号： H01L21302

    CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3185 ,  Y10S438/97

    摘要： A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.

    摘要翻译： 提供了用于SiO 2的反应离子蚀刻的方法和用于这种蚀刻中的蚀刻阻挡层。 具有小于约0.8且优选化学计量量为0.75的六至奈比（x：y）的氮化硅（SixNy）阻挡层对正移动离子污染提供优异的回弹性，但蚀刻选择性差。 然而，六至氮（x：y）的比例为1.0或更大的氮化硅阻挡层相对于SiO 2具有优异的蚀刻选择性，但对于移动离子污染的正面阻挡性差。 在掺杂硅衬底上形成氮化硅屏障，该阻挡层具有两个部分。 一个部分相对于二氧化硅具有比第二部分更大的蚀刻选择性，并且第二部分比第一部分具有更大的对正性可移动离子透射的抵抗力。 与硅衬底相邻的一个部分的硅氮比小于约0.8。 在第一部分顶部形成的第二部分形成硅与氮的比大于约0.8。 优选地，两个部分一起为约50至约100纳米厚。

    PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING
    7.
    发明申请
    PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING 有权
    相变式存储单元阵列与自适应底层电极及其制造方法

    公开(公告)号：US20120193599A1

    公开(公告)日：2012-08-02

    申请号：US13445194

    申请日：2012-04-12

    申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch

    发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch

    IPC分类号： H01L45/00

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

    摘要： An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.

    摘要翻译： 通过在触点阵列上形成分离层，在分离层上形成图形层并使用光刻工艺在图案形成层中形成掩模开口阵列来制造相变存储器单元的阵列。 通过补偿由平版印刷工艺产生的掩模开口的尺寸变化的过程，在掩模开口内形成蚀刻掩模。 蚀刻掩模用于蚀刻通过分离层以限定暴露下面的触点的电极开口的阵列。 电极材料沉积在电极开口内; 并且存储元件形成在底部电极上。 最后，在存储器元件上形成位线以完成存储器单元。 在所得到的存储器阵列中，底部电极的顶表面的临界尺寸小于掩模开口中存储元件的宽度。

    PCM with poly-emitter BJT access devices
    8.
    发明授权
    PCM with poly-emitter BJT access devices 有权
    PCM与多发射器BJT接入设备

    公开(公告)号：US08138574B2

    公开(公告)日：2012-03-20

    申请号：US12510588

    申请日：2009-07-28

    申请人： Tze-Chiang Chen ,  Chung Hon Lam ,  Bipin Rajendran

    发明人： Tze-Chiang Chen ,  Chung Hon Lam ,  Bipin Rajendran

    IPC分类号： H01L27/06

    CPC分类号： H01L45/1233 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06

    摘要： A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor.

    摘要翻译： 相变存储器（PCM）包括包括多个存储器单元的阵列，包括相变元件（PCE）的存储单元; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。 用于相变存储器（PCM）的存储单元包括相变元件（PCE）; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。

    Multi-bit memory error detection and correction system and method
    9.
    发明授权
    Multi-bit memory error detection and correction system and method 有权
    多位存储器错误检测和校正系统及方法

    公开(公告)号：US08055988B2

    公开(公告)日：2011-11-08

    申请号：US11694025

    申请日：2007-03-30

    申请人： Chung Hon Lam

    发明人： Chung Hon Lam

    IPC分类号： G06F11/00 ,  H03M13/00

    CPC分类号： G06F11/1072 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5678 ,  G11C13/0004 ,  G11C27/005 ,  G11C29/00 ,  G11C2211/5641

    摘要： A system and method for operating a collection of memory cells includes storing binary data values and parity data values by associating binary values with a common adjustable characteristic parameter of a memory cell collection. Probability distribution functions for values of the characteristic parameter of the memory cell collection are read and constructed. Binary data values and parity data values stored in the memory cell collection are retrieved. Parity data for error detection and error correction is evaluated in the binary data values.

    摘要翻译： 用于操作存储器单元的集合的系统和方法包括通过将二进制值与存储器单元集合的公共可调特性参数相关联来存储二进制数据值和奇偶校验数据值。 对存储单元集合的特性参数的值的概率分布函数进行读取和构造。 检索存储在存储单元集合中的​​二进制数据值和奇偶校验数据值。 用于错误检测和纠错的奇偶校验数据在二进制数据值中进行评估。