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1.发明授权Universal pointer implementation scheme for uniformly addressing distinct memory spaces in a processor's address space 有权通用指针实现方案，用于统一处理处理器地址空间中的不同存储空间公开(公告)号：US06658553B1
公开(公告)日：2003-12-02
申请号：US09548987
申请日：2000-04-14
申请人： Zhimin Ding , Gregory K. Goodhue , Ata R. Khan
发明人： Zhimin Ding , Gregory K. Goodhue , Ata R. Khan
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F9/342 , G06F12/0623
摘要： A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional memory-space dependent instructions, such as MOV, MOVX, and MOVC, provide an optimized addressing scheme, and an extended memory-space independent instruction EMOV provides an optimized code efficiency, processing speed, and ease of code generation. A mapping between the discrete memory space partitions and a “universal” memory space allocation is provided. The processing hardware interprets the universal address to determine the corresponding memory space, and provides the access to an address within that memory space.
摘要翻译： 处理系统支持基于不同存储器空间访问指令的存储器访问以及独立于存储器空间分区的通用访问指令。 传统的与存储器空间相关的指令，例如MOV，MOVX和MOVC，提供了优化的寻址方案，扩展的存储空间独立指令EMOV提供了优化的代码效率，处理速度和代码生成的便利性。 提供了离散存储器空间分区与“通用”存储器空间分配之间的映射。 处理硬件解释通用地址以确定相应的存储器空间，并提供对该存储器空间内的地址的访问。
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公开(公告)号：US06526463B1
公开(公告)日：2003-02-25
申请号：US09548988
申请日：2000-04-14
申请人： Zhimin Ding , Gregory K. Goodhue , Ata R. Khan
发明人： Zhimin Ding , Gregory K. Goodhue , Ata R. Khan
IPC分类号： G06F942
CPC分类号： G06F9/342 , G06F9/30043 , G06F9/30163 , G06F9/30189 , G06F9/4486 , G06F9/4812
摘要： A processing system with extended addressing capabilities includes a control bit that controls the number of address bytes that are stored onto a program stack. If the control bit is set to a first state, the address is pushed onto the program stack in the same manner as that used for shorter-address legacy devices. If the control bit is set to a second state, the address is pushed onto the program stack using the number of bytes required to contain a longer extended address. This same control bit controls the number of bytes that are popped off the stack upon return from an interrupt subroutine. The state of the control bit is controlled by one or more program instructions, thereby allowing it to assume each state dynamically. This dynamic control of the number of bytes pushed and popped to and from the stack allows for an optimization of stack utilization, and thereby further compatibility with legacy devices and applications.
摘要翻译： 具有扩展寻址能力的处理系统包括控制位，该控制位控制存储在程序堆栈上的地址字节数。 如果控制位设置为第一状态，则以与用于较短地址的传统设备相同的方式将地址推送到程序堆栈。 如果控制位设置为第二个状态，则使用包含较长扩展地址所需的字节数将该地址推送到程序堆栈。 相同的控制位控制从中断子程序返回时从堆栈弹出的字节数。 控制位的状态由一个或多个程序指令控制，从而允许其动态地呈现每个状态。 对堆栈和从堆栈进行弹出的字节数的这种动态控制允许优化堆栈利用率，从而进一步与传统设备和应用程序的兼容性。
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公开(公告)号：US06643755B2
公开(公告)日：2003-11-04
申请号：US09788692
申请日：2001-02-20
申请人： Gregory K. Goodhue , Ata R. Khan , John H. Wharton
发明人： Gregory K. Goodhue , Ata R. Khan , John H. Wharton
IPC分类号： G06F1200
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/381
摘要： A memory access architecture and technique employs multiple independent buffers that are configured to store items from memory sequentially. The memory is logically partitioned, and each independent buffer is associated with a corresponding memory partition. The partitioning is cyclically sequential, based on the total number of buffers, K, and the size of the buffers, N. The first N memory locations are allocated to the first partition; the next N memory locations to the second partition; and so on until the Kth partition. The next N memory locations, after the Kth partition, are allocated to the first partition; the next N locations are allocated to the second partition; and so on. When an item is accessed from memory, the buffer corresponding to the item's memory location is loaded from memory, and a prefetch of the next sequential partition commences to load the next buffer. During program execution, the ‘steady state’ of the buffer contents corresponds to a buffer containing the current instruction, one or more buffers containing instructions immediately following the current instruction, and one or more buffers containing instructions immediately preceding the current instruction. This steady state condition is particularly well suited for executing program loops, or a continuous sequence of program instructions, and other common program structures. The parameters K and N are selected to accommodate typically sized program loops.
摘要翻译： 存储器访问架构和技术采用多个独立缓冲器，其被配置为顺序存储来自存储器的项目。 存储器被逻辑地分区，并且每个独立的缓冲器与相应的存储器分区相关联。 基于缓冲区总数K和缓冲区N的大小，分区是循环的顺序。前N个存储器位置被分配给第一分区; 下一个N个存储器位置到第二个分区; 等等，直到第K个分区。 在第K个分区之后的下一个N个存储单元被分配给第一个分区; 接下来的N个位置被分配给第二分区; 等等。 当从存储器访问项目时，与存储器对应的缓冲区从存储器加载，并且下一个顺序分区的预取开始加载下一个缓冲区。 在程序执行期间，缓冲内容的“稳定状态”对应于包含当前指令的缓冲器，一个或多个缓冲区，其中包含紧跟在当前指令之后的指令，以及一个或多个缓冲区，其中包含紧邻当前指令之前的指令。 这种稳态条件特别适用于执行程序循环，或程序指令的连续序列以及其他通用程序结构。 选择参数K和N以适应通常尺寸的程序循环。
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4.发明授权Memory accelerator with two instruction set fetch path to prefetch second set while executing first set of number of instructions in access delay to instruction cycle ratio 有权存储器加速器具有两条指令集提取路径，用于在访问延迟到指令周期比率的同时执行第一组指令数时预取第二组公开(公告)号：US07290119B2
公开(公告)日：2007-10-30
申请号：US10923284
申请日：2004-08-20
IPC分类号： G06F9/28
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/381
摘要： A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into ‘stripes’, or ‘cyclically sequential’ partitions, and the memory accelerator module includes a latch that is associated with each partition. When a particular partition is accessed, it is loaded into its corresponding latch, and the instructions in the next sequential partition are automatically pre-fetched into their corresponding latch. In this manner, the performance of a sequential-access process will have a known response, because the pre-fetched instructions from the next partition will be in the latch when the program sequences to these instructions. Previously accessed blocks remain in their corresponding latches until the pre-fetch process ‘cycles around’ and overwrites the contents of each sequentially-accessed latch. In this manner, the performance of a loop process, with regard to memory access, will be determined based solely on the size of the loop. If the loop is below a given size, it will be executable without overwriting existing latches, and therefore will not incur memory access delays as it repeatedly executes instructions contained within the latches. If the loop is above a given size, it will overwrite existing latches containing portions of the loop, and therefore require subsequent re-loadings of the latch with each loop. Because the pre-fetch is automatic, and determined solely on the currently accessed instruction, the complexity and overhead associated with this memory acceleration is minimal.
摘要翻译： 存储器加速器模块使用确定性访问协议来缓冲用于高速访问的程序指令和/或数据。 程序存储器在逻辑上被划分为“条带”或“循环顺序”分区，并且存储器加速器模块包括与每个分区相关联的锁存器。 当访问特定分区时，它被加载到其对应的锁存器中，并且下一个顺序分区中的指令被自动预取到其对应的锁存器中。 以这种方式，顺序访问过程的性能将具有已知的响应，因为当程序对这些指令进行排序时，来自下一分区的预取指令将在锁存器中。 先前访问的块保留在其对应的锁存器中，直到预取处理“周转”并覆盖每个顺序访问的锁存器的内容。 以这种方式，关于存储器访问的循环处理的执行将仅基于循环的大小来确定。 如果循环低于一个给定的大小，它将可执行而不会覆盖现有的锁存器，因此它不会因为重复执行包含在锁存器内的指令而引起存储器访问延迟。 如果循环高于给定尺寸，它将覆盖包含循环部分的现有锁存器，因此需要随后每个循环重新加载锁存器。 因为预取是自动的，并且仅根据当前访问的指令确定，与该存储器加速相关联的复杂性和开销是最小的。
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5.发明授权Pin selection system for microcontroller having multiplexer selects between address/data signals and special signals produced by special function device 失效具有多路复用器的微控制器的引脚选择系统在地址/数据信号和特殊功能器件产生的特殊信号之间进行选择
公开(公告)号：US5787299A
公开(公告)日：1998-07-28
申请号：US751281
申请日：1996-11-18
CPC分类号： G06F1/22
摘要： A microcontroller with selectable function external pins. Program controllable configuration registers control pin function selection through multiplexers which select between data/address lines and special function unit output lines and which control line drivers which are disabled when the pins are used as input pins.
摘要翻译： 具有可选功能外部引脚的微控制器。 程序可控配置寄存器通过在数据/地址线和特殊功能单元输出线之间进行选择的多路复用器控制引脚功能选择，以及当引脚用作输入引脚时禁用的控制线驱动器。
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公开(公告)号：US20120084532A1
公开(公告)日：2012-04-05
申请号：US12895406
申请日：2010-09-30
CPC分类号： G06F12/0862
摘要： A microcontroller using an optimized buffer replacement strategy comprises a memory configured to store instructions, a processor configured to execute said program instructions, and a memory accelerator operatively coupled between the processor and the memory. The memory accelerator is configured to receive an information request and overwrite the buffer from which the prefetch was initiated with the requested information when the request is fulfilled by a previously initiated prefetch operation.
摘要翻译： 使用优化的缓冲器替换策略的微控制器包括被配置为存储指令的存储器，被配置为执行所述程序指令的处理器以及可操作地耦合在处理器和存储器之间的存储器加速器。 存储器加速器被配置为当通过先前发起的预取操作来满足请求时，接收信息请求并覆盖从所请求的信息发起预取的缓冲器。
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7.发明授权System for write protecting a bit that is hardware modified during a read-modify-write cycle 失效用于写保护的系统在读 - 修改 - 写周期期间修改硬件的位
公开(公告)号：US5655135A
公开(公告)日：1997-08-05
申请号：US308059
申请日：1994-09-16
CPC分类号： G06F9/30094 , G06F11/004 , G11C7/00
摘要： In a computer system, especially a microcontroller, a circuit for protecting hardware-modifiable status bits during a read-modify-write operation, which circuit is relatively simple to implement yet operates well and does not require an undue amount of die real estate to implement. The circuit comprises means for storing information representing whether a hardware-modifiable status bit has been updated during a read-modify-write operation, and means to prevent over-writing of the status bit during the write portion of the read-modify-write cycle when the stored information is detected. The means for storing the information comprises a latch set into its first state whose output indicates whether the first state exists. That output is connected to logic circuitry which blocks the rewrite portion of the read-modify-write operation from changing a hardware-modified bit set during that cycle.
摘要翻译： 在计算机系统，特别是微控制器中，用于在读取 - 修改 - 写入操作期间保护硬件可修改状态位的电路，哪个电路相对简单地实现，但是运行良好并且不需要不必要的数量的裸片空间来实现 。 该电路包括用于存储表示在读 - 修改 - 写操作期间是否更新硬件可修改状态位的信息的装置，以及用于防止在读 - 修改 - 写周期的写入部分期间重写状态位的装置 当检测到存储的信息时。 用于存储信息的装置包括一个锁存器组，其中第一状态的输出指示第一状态是否存在。 该输出连接到逻辑电路，其阻止读 - 修改 - 写操作的重写部分在该周期期间改变硬件修改的位集合。
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公开(公告)号：US5619663A
公开(公告)日：1997-04-08
申请号：US308051
申请日：1994-09-16
CPC分类号： G06F9/3814 , G06F12/0215 , G06F9/3802
摘要： An instruction prefetch system for a digital processor, and in particular a microcontroller which includes the prefetch system and instruction queue normally provided as part of the instruction fetch unit, to which is added a second instruction prefetch buffer in the system, preferably in the bus interface unit which serves as the memory interface unit. This added prefetch buffer has storage for only a small number of bytes or words, and operates to supply prefetched instructions to the queue in the instruction fetch unit. However, it operates under the following constraint: it only prefetches within the boundaries of each small block of code memory and stalls when a block boundary is reached until a new address appears. This approach combines some cache and prefetch principles for a limited cost design.
摘要翻译： 一种用于数字处理器的指令预取系统，特别是包括通常作为指令获取单元的一部分提供的预取系统和指令队列的微控制器，其中在系统中添加了第二指令预取缓冲器，优选地在总线接口 作为存储器接口单元的单元。 这个添加的预取缓冲区只有少量的字节或字存储，并且操作以在指令获取单元中向队列提供预取指令。 然而，它在以下约束下操作：它仅在每个小块代码存储器的边界内预取，并且当达到块边界直到新的地址出现时停止。 这种方法结合了有限成本设计的一些缓存和预取原则。
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9.发明授权High speed memory access system for a microcontroller with directly driven low order address bits 失效具有直接驱动低位地址位的微控制器的高速存储器存取系统
公开(公告)号：US5594913A
公开(公告)日：1997-01-14
申请号：US308060
申请日：1994-09-16
CPC分类号： G11C8/00 , G06F12/0215
摘要： A microcontroller which directly drives a memory with low order address bits during a fetch operation. Driving the low order address bits directly while the high order bits are latched during an address/data multiplex on the same pins allows the latch enable cycle to be skipped during sequential fetches. A sequential address detector indicates when the latch enable cycle can be skipped.
摘要翻译： 在提取操作期间直接驱动低位地址位的存储器的微控制器。 在同一个引脚的地址/数据多路复用期间，直接驱动低位地址位，同时在地址/数据多路复用期间锁存高位位允许在顺序读取期间跳过锁存使能周期。 顺序地址检测器指示何时可以跳过锁存使能周期。
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公开(公告)号：US4905137A
公开(公告)日：1990-02-27
申请号：US136249
申请日：1987-12-18
CPC分类号： G06F12/0623 , G06F12/0215
摘要： Page-mode-organized ROMs and associated circuitry are connected only to data and control buses in an information processing system. Addressing and reading of the ROMs are controlled by a processor without connecting the ROMs to an address bus. Selection of a particular ROM and of a particular page in the selected ROM is accomplished by applying a first control signal to the control bus and a first data word to the data bus. This first data word thus serves as the address of the selected page in the selected ROM. Then a particular byte of the selected page is selected by applying a second control signal to the control bus and a second data word to the data bus. This second data word serves as the address of the selected byte. Subsequently, in response to a third control signal, the selected byte is read out of the selected ROM and applied to the data bus.
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