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公开(公告)号：US20240049443A1
公开(公告)日：2024-02-08
申请号：US17881969
申请日：2022-08-05
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： Approaches for reducing GIDL are disclosed. In one example, a method of forming a DRAM device may include forming a trench in a substrate layer, providing a first gate oxide layer along a sidewall and a bottom surface of the trench, and forming a first gate material within the trench. The method may further include removing the first gate oxide layer along an upper portion of the sidewall of the trench by delivering ions into the upper portion of the trench at a non-zero angle relative to a perpendicular extending from an upper surface of the substrate layer, and forming a second gate oxide layer along the upper portion of the sidewall of the trench, wherein a first dielectric constant of the first gate oxide layer is greater than a second dielectric constant of the second gate oxide layer.
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公开(公告)号：US11942361B2
公开(公告)日：2024-03-26
申请号：US17348093
申请日：2021-06-15
IPC分类号： H01L21/768 , H01L21/02 , H01L21/764
CPC分类号： H01L21/7682 , H01L21/0226 , H01L21/764
摘要： Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.
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公开(公告)号：US11987879B2
公开(公告)日：2024-05-21
申请号：US17673667
申请日：2022-02-16
发明人： Armin Saeedi Vahdat , Yan Zhang , John Hautala
IPC分类号： H01L21/306 , C23C14/48 , C23C16/30 , C23C16/40 , C23C16/513 , C23C28/04 , H01L21/3065
CPC分类号： C23C16/303 , C23C14/48 , C23C16/40 , C23C16/513 , C23C28/04 , H01L21/30604 , H01L21/30621 , H01L21/3065
摘要： Disclosed are approaches for forming semiconductor device cavities. One method may include providing a set of semiconductor structures defining an opening, wherein the opening has a first opening width along an upper portion of the opening and a second opening width along a lower portion of the opening, the first opening width being greater than the second opening width. The method may further include forming a blocking layer along the set of semiconductor structures by delivering a material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the set of semiconductor structures. The blocking layer may be formed along the upper portion of the opening without being formed along the lower portion of the opening, and wherein an opening through the blocking layer is present above the opening.
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公开(公告)号：US20220399225A1
公开(公告)日：2022-12-15
申请号：US17348093
申请日：2021-06-15
IPC分类号： H01L21/768 , H01L21/02 , H01L21/764
摘要： Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.
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公开(公告)号：US12096622B2
公开(公告)日：2024-09-17
申请号：US17502140
申请日：2021-10-15
IPC分类号： H10B41/20 , B82Y10/00 , B82Y40/00 , H10B41/23 , H10B41/27 , H10B41/41 , H10B43/20 , H10B43/23 , H10B43/27 , H10B43/40
摘要： A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.
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公开(公告)号：US11778832B2
公开(公告)日：2023-10-03
申请号：US17306047
申请日：2021-05-03
摘要： Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.
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公开(公告)号：US20230257872A1
公开(公告)日：2023-08-17
申请号：US17673667
申请日：2022-02-16
发明人： Armin Saeedi Vahdat , Yan Zhang , John Hautala
IPC分类号： C23C16/30 , C23C16/40 , H01L21/306 , C23C28/04
CPC分类号： C23C16/303 , C23C16/40 , H01L21/30621 , C23C28/04
摘要： Disclosed are approaches for forming semiconductor device cavities. One method may include providing a set of semiconductor structures defining an opening, wherein the opening has a first opening width along an upper portion of the opening and a second opening width along a lower portion of the opening, the first opening width being greater than the second opening width. The method may further include forming a blocking layer along the set of semiconductor structures by delivering a material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the set of semiconductor structures. The blocking layer may be formed along the upper portion of the opening without being formed along the lower portion of the opening, and wherein an opening through the blocking layer is present above the opening.
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公开(公告)号：US20230119618A1
公开(公告)日：2023-04-20
申请号：US17502140
申请日：2021-10-15
IPC分类号： H01L27/11551 , H01L27/11578 , H01L27/11573 , H01L27/11529
摘要： A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.
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公开(公告)号：US20220352182A1
公开(公告)日：2022-11-03
申请号：US17306047
申请日：2021-05-03
IPC分类号： H01L27/1157 , H01L27/11524 , H01L27/11551 , H01L27/11578 , G11C8/14
摘要： Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.
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