公开(公告)号：US11615225B2

公开(公告)日：2023-03-28

申请号：US17023153

申请日：2020-09-16

申请人： Synopsys, Inc.

发明人： In-Ho Moon

IPC分类号： G06F7/72 ,  G06F7/44 ,  G06F30/367 ,  G06F30/327 ,  G06F9/451

摘要： A system performs logic simulation of a circuit design specified using a hardware description language such as Verilog. The system performs constraint solving based on an expression specified in the specification of the circuit design. The system identifies required bits for each variable in the expression. The number of required bits is less than the number of bits specified in the variable declaration. The system performs bit-level constraint solving by performing a bit operation on the set of required bits and a simplified processing of the remaining bits of the variable. Since the original circuit design is preserved with the original bit-widths for simulation, those required bits are used on the fly internally during constraint solving. Furthermore, dynamic bit reductions on arithmetic operations are performed on the fly. The system improves computational efficiency by restricting bit operations to fewer bits of variables and operators of the expression.

公开(公告)号：US11610038B2

公开(公告)日：2023-03-21

申请号：US16042952

申请日：2018-07-23

申请人： Assurant Design Automation LLC

发明人： M. David McFarland

IPC分类号： G06F30/327 ,  G06F17/18 ,  G06F9/46 ,  G06F111/08

摘要： For risk evaluation, a method encodes event data as a linear array that includes a plurality of logic states. The method estimates a success probability for each logic state and identifies path groups of the plurality of logic states. The logic states of each path group must all be healthy for each logic state to contribute to system success. The method further identifies each path combination of path groups and path nodes that result in system success. In addition, the method calculates a system success probability as a sum of success probabilities for each path combination. The success rate for each path combination is calculated as a product of the path group success probabilities for the path combination.

公开(公告)号：US20230077532A1

公开(公告)日：2023-03-16

申请号：US17946761

申请日：2022-09-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Wookyu KIM ,  Changbeom Kim ,  Taejun Yoo ,  Seungmin Lee

IPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/327

摘要： A standard cell and an integrated circuit including the same are is provided. The standard cell is provided in first and second rows. The standard cell includes: a first circuit region provided in the first row and including a plurality of first transistors; a second circuit region provided in the second row and including a plurality of second transistors; a first input pin provided in the first circuit region and configured to receive a first input signal; and a second input pin provided in the second circuit region and configured to receive a second input signal. The first input signal is input to gate terminals of each of the plurality of first transistors, and the second input signal is input to gate terminals of each of the plurality of second transistors. The first circuit region is symmetric with respect to a second horizontal direction and the second circuit region is symmetric with respect to the second horizontal direction.

公开(公告)号：US20230071521A1

公开(公告)日：2023-03-09

申请号：US17897085

申请日：2022-08-26

申请人： Synopsys, Inc.

发明人： Mohan Mangal ,  Rohit Kumar Ohlayan ,  Himanshu Kathuria ,  Jaskaran Singh Ajimal

IPC分类号： G06F30/327 ,  G06F30/3308 ,  G06F30/3315

摘要： A system receives a specification of a circuit design for performing simulation of the circuit design. The specification includes one or more prototyping statements. A prototyping statement is processed by simulation of the circuit design. The system generates a netlist graph based on the specification of the circuit design. The system ignores the prototyping statements while generating the netlist graph. The system modifies the netlist graph to incorporate the prototyping statements of the specification. The netlist graph is modified by adding at least a net to the netlist graph based on a prototyping statement. The system performs static analysis based on the modified netlist graph.

公开(公告)号：US20230061099A1

公开(公告)日：2023-03-02

申请号：US17893975

申请日：2022-08-23

申请人： Mark Cummings

发明人： Mark Cummings

IPC分类号： H04W24/02 ,  G06F30/327 ,  G06F9/4401 ,  H04L67/10 ,  H04W8/22 ,  H04W28/02 ,  H04W48/16 ,  H04L67/51 ,  H04L67/50 ,  G06F21/55

摘要： An alert that is generated by a first orchestrator associated with a first subsystem or received from one or more distributed orchestrators that are associated with one or more corresponding subsystems is analyzed. The alert is triggered by a change in behavior determined by a behavioral analysis algorithm associated with the first orchestrator or corresponding behavior analysis algorithms associated with the one or more distributed orchestrators. It is determined whether an alert is indicative of a false positive based on an objective associated with the first orchestrator, an algorithm associated with the first orchestrator and one or more constraints associated with the first orchestrator. The alert is filtered in response to determining that the alert is indicative of the false positive.

公开(公告)号：US20230044517A1

公开(公告)日：2023-02-09

申请号：US17817904

申请日：2022-08-05

申请人： Battelle Memorial Institute

发明人： Timothy A. McDonley ,  Andrew Elliott ,  Adam Kimura ,  Katie T. Liszewski ,  Thomas Kent ,  Josh Delozier ,  Benjamin Hayden

IPC分类号： G06F30/327 ,  G06F30/337

摘要： The present disclosure provides a method for generating a spatially resolved netlist that includes generating a netlist based on integrated circuit (IC) layout data and standard cell library data, the netlist including cell and net definitions associated with the IC; determining position data for respective cells and nets based on the IC layout data; mapping the position data to respective cell and net definitions in the netlist; and generating a spatially resolved netlist that includes the mapped position data to respective cell and net definitions.

公开(公告)号：US20230043751A1

公开(公告)日：2023-02-09

申请号：US17868325

申请日：2022-07-19

申请人： Synopsys, Inc.

发明人： Zamrath NIZAM ,  Chirath Chamikara DIYAGAMA ,  Bhaskar PAL ,  Ashan WICKRAMASINGHE

IPC分类号： G06F30/33 ,  G06F30/327

摘要： A method is provided. The method includes obtaining, for a particular integrated (IC) design, register transfer level (RTL) code and unified power format (UPF) settings, generating an RTL feature array from the RTL code, arranging features based on a UPF into a UPF feature array, generating, by a processor, a combined feature array for the particular IC design by combining the RTL feature array and the UPF feature array, comparing the combined feature array for the particular IC design with another combined feature array, and reporting differences, based on the comparing, between the combined feature array and the other combined feature array to identify changes in at least one of the RTL code and the UPF settings that resulted in a change in a number of power violations.

公开(公告)号：US20230015367A1

公开(公告)日：2023-01-19

申请号：US17944379

申请日：2022-09-14

申请人： Samsung Electronics Co., Ltd.

发明人： Raheel Azmat ,  Sidharth Rastogi ,  Chul-hong Park ,  Jae-seok Yang ,  Kwan-young Chun

IPC分类号： G06F30/327 ,  H01L27/02 ,  G06F30/398

摘要： An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

公开(公告)号：US11544433B1

公开(公告)日：2023-01-03

申请号：US17389570

申请日：2021-07-30

申请人： Diakopto, Inc.

发明人： Maxim Ershov ,  Andrei Tcherniaev

IPC分类号： G06F30/31 ,  G06F30/327

摘要： A computer/software tool for electronic design automation (EDA) uses parasitic elements from a post-layout netlist (PLN) file for a given IC design to assess routing-imposed RC-based signal degeneration. The computer/software tool facilitates selection of, and insertion location for, one or more “virtual repeaters,” based on modification to the PLN file. The tool generates a visual display based on the calculated design characteristics, facilitating adjustment and optimization of repeater cell and location by the designer. The repeater insertion is “virtual,” because modeling and adjustment can be based on abstractions (e.g., load capacitance presented by a repeater) and the already-extracted netlist file, and because an actual circuit design need not be created until after a designer has fine-tuned repeater insertion parameters.

公开(公告)号：US20220414439A1

公开(公告)日：2022-12-29

申请号：US17892876

申请日：2022-08-22

申请人： SYNTIANT

发明人： Pieter Vorenkamp ,  Kurt F. Busch ,  Stephen W. Bailey ,  Jeremiah H. Holleman, III

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/10 ,  G06N3/08 ,  G06F30/36 ,  G06F30/327 ,  H01L21/82

摘要： Disclosed herein is a method for automatically generating an integrated circuit. The method includes receiving a behavioral description of at least the first layer of the neural network, converting the behavioral description of the first layer of the neural network into the computational graph, converting a computational graph to a circuit netlist based on a correlation of: (i) operations described in the computational graph, and (ii) an analog cell library including a plurality of predetermined circuit blocks that describe known neural network operations, generating a circuit layout that corresponds to at least a first layer of a neural network, and performing additional actions configured to cause generation of the integrated circuit based on the circuit layout. In some situations, the behavioral description defines an architecture of machine learning logic that represents at least a portion of the neural network. Additionally, in some situations, each cell of the integrated circuit includes a metal-oxide-semiconductor field-effect transistor (“MOSFET”).