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公开(公告)号：US20240364265A1
公开(公告)日：2024-10-31
申请号：US18029173
申请日：2022-03-23
发明人： Junwei GUO , Feng QU , Biqi LI
IPC分类号： H03D7/14 , H03K5/1252 , H03K21/00
CPC分类号： H03D7/1458 , H03K5/1252 , H03K21/00
摘要： The present disclosure provides a frequency generator, and belongs to the technical field of communications. The frequency generator provided by the present disclosure includes: N stages of mixing modules and N stages of comb spectrum generation modules. Each of the comb spectrum generation modules is configured to provide a mixing module in a same stage as the comb spectrum generation modules with one stage of fundamental signal group generated according to a second reference signal; and different stages of fundamental signal groups are generated based on different second reference signals. A 1st-stage mixing module generates a 1st-stage mixed signal according to a 1st-stage fundamental signal group and a first reference signal, and the 1st-stage fundamental signal group includes a plurality of harmonic signals with a first frequency as a fundamental frequency.
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公开(公告)号：US20240275369A1
公开(公告)日：2024-08-15
申请号：US18647662
申请日：2024-04-26
申请人： Apple Inc.
发明人： Helena Deirdre O'SHEA , Dmitry CHERNIAVSKY , Tim SCHOENAUER , Ali MOAZ , Rahmi HEZAR , Ram KANUMALLI
IPC分类号： H03K5/1252 , G06F1/08 , G06F13/40
CPC分类号： H03K5/1252 , G06F1/08 , G06F13/4027
摘要： Embodiments relate to updating spur cancellation at a victim integrated circuit (IC) in accordance with dynamic changes in the operating frequencies of an aggressor IC. The aggressor IC changes its operating frequencies at an update time that is determined in advance. The update time and the changes to the operating frequencies are shared with the victim IC. The victim IC dynamically updates the relationships between frequencies of local clock signals for the victim IC and the aggressor IC. The victim IC generates a spur cancellation parameter based on the updated relationships of local clock frequencies, the update time and the changes to the operating frequencies of the aggressor IC, and configures a spur cancellation circuit. In this way, the victim IC may perform effective spur cancellation despite changes in the operating frequencies of the aggressor IC and deviation of the local clock frequencies.
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公开(公告)号：US12057841B1
公开(公告)日：2024-08-06
申请号：US18173822
申请日：2023-02-24
发明人： Bal S. Sandhu
CPC分类号： H03K3/0377 , H03K5/1252 , H03K5/133 , H03K5/135 , H03K21/00
摘要： A circuit receives an input clock pulse signal characterized by a first frequency and a first pulse width, and produces an output pulse signal characterized by a second frequency that is half of the first frequency and a second pulse width that is equal to the first pulse width. The circuit also includes a first D-flipflop, a first inverter, a first Schmitt trigger, and a first AND gate. The first D-flipflop includes a clock input terminal for receiving the input clock pulse signal and an output terminal for producing a first data output. The first inverter couples the output terminal and a data input terminal of the first D-flipflop. A first Schmitt trigger receives the input clock pulse signal and provides a first delayed input clock signal. The first AND gate receives the first data output and the first delayed input clock signal, and provides the output pulse signal.
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公开(公告)号：US20240195395A1
公开(公告)日：2024-06-13
申请号：US18424056
申请日：2024-01-26
IPC分类号： H03K5/1252
CPC分类号： H03K5/1252
摘要： Described are a circuit for compensating non-linearities essentially without changing a characteristic curve operating point and/or operating range, having: an alternating voltage signal source for providing an input signal; a control unit which receives the input signal and converts it to a predistorted signal depending on at least one preset predistortion parameter; and a sink for receiving the predistorted signal, the sink being coupled to an adjusting unit configured to provide the sink with an adjusting signal, to operate the sink in an operating range or at an operating point, the control unit being configured to receive at least one sensor signal of the sink in a feedback manner and to adapt the at least one preset predistortion parameter based on the at least one sensor signal, and a corresponding method.
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公开(公告)号：US20240178825A1
公开(公告)日：2024-05-30
申请号：US18462733
申请日：2023-09-07
发明人： Mark A. Wolfe , Harsh D. Jhaveri
IPC分类号： H03K5/14 , H03K5/1252 , H03K19/003
CPC分类号： H03K5/14 , H03K5/1252 , H03K19/00346
摘要： A circuit including a device including a receiver having a receiver input, a receiver output, and a bias current input and a bias generator having a bias current output coupled to the bias current input. The device also includes a buffer having a buffer input, an enable input, and a buffer output, the buffer input coupled to the receiver output and a delay circuit having a delay output coupled to the enable input.
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公开(公告)号：US20240146289A1
公开(公告)日：2024-05-02
申请号：US18496364
申请日：2023-10-27
发明人： Kun Wang
IPC分类号： H03K5/1252 , H01Q23/00
CPC分类号： H03K5/1252 , H01Q23/00 , H03H11/02
摘要： In accordance with an embodiment, A device includes: a first node configured to be coupled to a component to be tuned; a second node configured to be coupled to an inductor; a path including a capacitor coupling the first node and the second node; and a first switch coupled between the second node and a ground node.
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公开(公告)号：US11855641B2
公开(公告)日：2023-12-26
申请号：US17113501
申请日：2020-12-07
发明人： Oren Shlomo
IPC分类号： G01K7/18 , H03K5/1252 , H03K5/153 , H03K5/19 , G11C7/20 , H03K17/24 , G11C7/02 , H03K17/22 , G01K7/20 , G05F1/648 , G01R19/25 , G11C7/10 , G11C7/14 , H03K5/24
CPC分类号： H03K5/1252 , G01K7/183 , G01K7/20 , G01R19/2506 , G05F1/648 , G11C7/02 , G11C7/1039 , G11C7/14 , G11C7/20 , H03K5/153 , H03K5/19 , H03K5/2472 , H03K17/223 , H03K17/24
摘要： A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n−1, and the third number is 1, the total number of resistors is 2n.
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8.发明公开公开(公告)号：US20230412158A1
公开(公告)日：2023-12-21
申请号：US18037977
申请日：2021-10-20
申请人： ZTE CORPORATION
发明人： Bei HUANG , Zhilin CHEN
IPC分类号： H03K5/1252 , H03K5/00
CPC分类号： H03K5/1252 , H03K5/00006
摘要： A method and device for outputting frequency multiplication signal having high harmonic suppression, and a storage medium. The method includes: obtaining initial signal; inputting the initial signal into target circuit, where the target circuit includes parallel circuit, first circuit of the parallel circuit is provided with frequency multiplier, second circuit of the parallel circuit is provided with phase adjustment module, the first circuit is connected to input end and output ends of the target circuit, the second circuit is disconnected from the input end and the output end, the phase adjustment module is configured to adjust a phase of the second circuit to a target phase, and phase difference between the target phase and a first phase of the first circuit is greater than 90 degrees; taking a target signal output from the target circuit as frequency multiplication signal of the initial signal.
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公开(公告)号：US11764780B2
公开(公告)日：2023-09-19
申请号：US17960213
申请日：2022-10-05
申请人： NEC Corporation
发明人： Aiko Yamaguchi , Yuichi Igarashi
IPC分类号： H03K17/92 , H03K5/1252
CPC分类号： H03K17/92 , H03K5/1252
摘要： In an aspect, the present disclosure provides a superconducting circuit including: a ground plane including a superconducting member; a plurality of superconducting parts surrounded by a non-conductive part with space from the ground plane, each of the plurality of superconducting parts including four coupling ports each configured to enable the superconducting part to interact with another superconducting part; a superconducting quantum interference device configured to set a resonance frequency of a first superconducting part included in the plurality of superconducting parts; and a multilevel wiring line configured to form, in cooperation with the ground plane, a superconducting loop surrounding the superconducting quantum interference device, in which the superconducting quantum interference device is disposed, in an area inside the superconducting loop, at a place where a magnetic field generated by a current from a bias line for the first superconducting part is applied.
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10.发明授权公开(公告)号：US11764771B2
公开(公告)日：2023-09-19
申请号：US17970165
申请日：2022-10-20
发明人： Cheng-Chieh Wang
IPC分类号： H03K3/00 , H03K5/153 , H03K3/017 , H03K5/1252 , H03K3/011 , H03K3/013 , H03K5/04 , G06F21/75
CPC分类号： H03K5/153 , H03K3/011 , H03K3/013 , H03K3/017 , H03K5/04 , H03K5/1252 , G06F21/755
摘要： An event detection controller for a circuit system controlled by a pulse wave modulation signal, can perform a specific event handling when a specific event is detected, wherein the specific event handling includes stopping a pulse wave modulation device, starting up the stopped pulse wave modulation device, controlling the pulse wave modulation device to change the pulse wave modulation signal, outputting a wake-up signal to wake up the circuit system, controlling the pulse detector to change its detection configuration, changing a cumulative occurrences number of the specific pattern of an event discrimination module, outputting a control signal or a first data signal to a peripheral device through a bus connected to an event response module and/or requesting the peripheral device to send a second data signal through the bus.
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