公开(公告)号：WO2016141060A1

公开(公告)日：2016-09-09

申请号：PCT/US2016/020455

申请日：2016-03-02

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： CHEN, Chung-Ming ,  YANG, Jeng-Wei ,  SU, Chien-Sheng ,  WU, Man-Tang ,  DO, Nhan

IPC: H01L21/28 ,  G11C16/04 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L27/11531 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device comprises a semiconductor substrate with memory (16) and logic device areas (18). A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices are formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

Abstract translation: 存储器件包括具有存储器（16）和逻辑器件区域（18）的半导体衬底。 多个存储单元形成在存储区域中，每个存储单元包括第一源极和漏极区域，其间具有第一沟道区域，布置在第一沟道区域的第一部分上方的浮置栅极，设置在浮置栅极上的控制栅极， 设置在第一通道区域的第二部分上的选择栅极和设置在源极区域上的擦除栅极。 多个逻辑器件形成在逻辑器件区域中，每个逻辑器件包括其间具有第二沟道区的第二源极和漏极区域以及设置在第二沟道区域上的逻辑门极。 衬底上表面在存储器区域中比在逻辑器件区域中凹陷更低，使得较高的存储器单元具有与逻辑器件类似的上部高度。

公开(公告)号：WO2016118532A1

公开(公告)日：2016-07-28

申请号：PCT/US2016/013966

申请日：2016-01-19

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： WU, Man-Tang ,  YANG, Jeng-Wei ,  SU, Chien-sheng ,  CHEN, Chun-Ming ,  DO, Nhan

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L29/66537 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.

Abstract translation: 一种在具有存储器，LV和HV区域的衬底上形成存储器件的方法，包括在存储区域中形成间隔开的存储堆叠对，在衬底上形成第一导电层并与衬底绝缘，在第一绝缘层上形成第一绝缘层 第一导电层并将其从存储器和HV区域中移除，执行导电材料沉积以增厚存储器和HV区域中的第一导电层，并在LV区域的第一绝缘层上形成第二导电层， 蚀刻以使存储器和HV区域中的第一导电层变薄，并且去除LV区域中的第二导电层，从LV区域移除第一绝缘层，以及图案化第一导电层以形成第一导电层的块 记忆，LV和HV区域。

公开(公告)号：WO2014149638A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/020015

申请日：2014-03-03

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： DO, Nhan ,  TRAN, Hieu, Van ,  SU, Chien, Sheng ,  TUNTASOOD, Prateep

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device array with spaced apart parallel isolation regions (128) is formed in a semiconductor substrate (12), with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions (16) with a channel region (18) therebetween, a floating gate (22) over a first channel region portion, and a select gate (20) over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches.

Abstract translation: 具有间隔开的平行隔离区域（128）的存储器件阵列形成在半导体衬底（12）中，每对相邻隔离区域之间具有有源区。 每个隔离区域包括形成在衬底表面中的沟槽和形成在沟槽中的绝缘材料。 绝缘材料的顶表面的部分凹陷在基底的表面下方。 每个有源区域包括一列存储单元，每个存储单元具有间隔开的第一和第二区域（16），其间具有沟道区域（18），在第一沟道区域部分上方的浮置栅极（22）和超过 第二通道区域部分。 选择栅极形成为垂直于隔离区域延伸的连续字线，并且每个形成用于一行存储器单元的选择栅极。 每个字线的部分向下延伸到沟槽中。

公开(公告)号：WO2014051855A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/052846

申请日：2013-07-31

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： TADAYONI, Mandana ,  DO, Nhan

IPC: G11C11/34

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/1054 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/788

Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

Abstract translation: 一种存储器件及其制造方法，具有第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，衬底中的沟道区域，导电浮动 栅极覆盖并与衬底绝缘，其中浮置栅极至少部分地设置在沟道区域的第一部分和沟槽区域的第一部分之上，导电第二栅极横向邻近并与浮动栅极绝缘，其中第二栅极被布置 至少部分地覆盖并与沟道区的第二部分绝缘，以及形成在第二栅极下方的衬底中的嵌入碳化硅的应力区域。

公开(公告)号：WO2013074250A2

公开(公告)日：2013-05-23

申请号：PCT/US2012/061387

申请日：2012-10-22

Applicant: SILICON STORAGE TECHNOLOGY, INC. ,  GHAZAVI, Parviz ,  TRAN, Hieu Van ,  WANG, Shiuh-Luen ,  DO, Nhan ,  OM'MANI, Henry A.

Inventor： GHAZAVI, Parviz ,  TRAN, Hieu Van ,  WANG, Shiuh-Luen ,  DO, Nhan ,  OM'MANI, Henry A.

IPC: H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7885

Abstract: An array of non-volatile memory cells has a semiconductor substrate of a first conductivity type with a top surface. A plurality of spaced apart first regions of a second conductivity type are in the substrate along the top surface. Each first region extends in a row direction. A plurality of spaced apart second regions of the second conductivity type are in the substrate along the top surface. Each second region is spaced apart from an associated first region in a column direction, perpendicular to the row direction. A channel region is defined between each second region and its associated first region in the column direction. Each channel region has a first portion and a second portion. A plurality of spaced apart word line gates extend in the row direction. Each word line gate is positioned over and is insulated from the first portion of a channel region, with each first portion of channel region immediately adjacent to the second region. A plurality of spaced apart floating gates are positioned over the second portions of the channel regions and are insulated therefrom. A plurality of spaced apart coupling gates extend in the row direction, with each coupling gate extending over and insulated from a plurality of floating gates. A plurality of spaced apart metal strapping lines extend in the row direction, with each metal strapping line associated with and overlying a coupling gate. A first metal strapping line is in a first row electrically connected to the associated underlying coupling gate in a plurality of first locations. A second metal strapping line is in a row immediately adjacent to the first row electrically connected to the associated underlying coupling gate in a plurality of second locations. The first locations and the second locations are not in the same column. A plurality of spaced apart erase gates extend in the row direction, with each erase gate positioned over a first region and insulated therefrom, and adjacent to and insulated from a floating gate and coupling gate.

Abstract translation: 一组非易失性存储单元具有具有顶表面的第一导电类型的半导体衬底。 多个间隔开的第二导电类型的第一区域沿着顶表面位于衬底中。 每个第一区域沿行方向延伸。 第二导电类型的多个间隔开的第二区域沿着顶表面位于衬底中。 每个第二区域与垂直于行方向的列方向上的相关联的第一区域间隔开。 在列方向上的每个第二区域和其相关联的第一区域之间限定沟道区域。 每个通道区域具有第一部分和第二部分。 多个间隔开的字线门在行方向上延伸。 每个字线栅极位于通道区域的第一部分上方并且与沟道区域的第一部分绝缘，沟道区域的每个第一部分紧邻第二区域。 多个间隔开的浮动栅极位于沟道区域的第二部分上方并与之绝缘。 多个间隔开的耦合栅极在行方向上延伸，每个耦合栅极延伸并且与多个浮动栅极绝缘。 多个间隔开的金属捆绑线在行方向上延伸，每个金属捆扎线与耦合栅极相关联并且覆盖在耦合栅极上。 第一金属捆绑线在第一排中，电连接到多个第一位置中的相关联的底部耦合栅极。 第二金属捆绑线在与多个第二位置中电连接到相关联的底部耦合栅极的第一行紧邻的行中。 第一个位置和第二个位置不在同一列中。 多个间隔开的擦除栅极在行方向上延伸，每个擦除栅极位于第一区域上方并与之绝缘，并且与浮栅和耦合栅极相邻并与其隔离。

公开(公告)号：WO2013052639A2

公开(公告)日：2013-04-11

申请号：PCT/US2012/058713

申请日：2012-10-04

Applicant: FLEXSTEEL PIPELINE TECHNOLOGIES, INC. ,  HEGLER, Matthew, Allen ,  HEATON, Andrew, James

Inventor： HEGLER, Matthew, Allen ,  HEATON, Andrew, James

IPC: F16L13/02

CPC classification number: F16L35/00 ,  F16L9/19 ,  F16L13/02 ,  F16L33/2071 ,  F16L39/005 ,  Y10T29/49879 ,  Y10T29/49968

Abstract: A pipe end fitting assembly that includes an outer body having an outer surface, an inner surface defining a first bore, and an end surface, and an inner body having an inner surface defining a second bore and an outer surface. A portion of the inner body outer surface is secured to the outer body inner surface. A passage formed in the outer body includes a first portion extending from the end surface and parallel to the first bore, and a second portion extending from the outer body outer surface to the passage first portion. A pipe end is disposed around and secured to a portion of the inner body outer surface. A jacket is disposed around the pipe and has an end secured to the outer body outer surface. The passage portions are in fluid communication with each other and a space between the jacket and the pipe.

Abstract translation: 一种管端装配组件，其包括具有外表面的外体，限定第一孔的内表面和端表面，以及具有限定第二孔和外表面的内表面的内体。 内体外表面的一部分固定在外体内表面上。 形成在外体中的通道包括从端面延伸并平行于第一孔的第一部分和从外体外表面延伸到通道第一部分的第二部分。 管端设置在内体外表面的一部分周围并固定。 护套设置在管子周围并且具有固定到外体外表面的端部。 通道部分彼此流体连通并且夹套与管道之间的空间。

公开(公告)号：WO2012106498A1

公开(公告)日：2012-08-09

申请号：PCT/US2012/023591

申请日：2012-02-02

Applicant: 1020, INC. ,  BEZANCON, Anne ,  PARKES, Daniel ,  BLAIR, Sweeden, A.

Inventor： BEZANCON, Anne ,  PARKES, Daniel ,  BLAIR, Sweeden, A.

IPC: G06Q30/00

CPC classification number: G06Q30/0255 ,  G06Q30/0261 ,  G06Q30/0269

Abstract: A method and system for communicating promotional offers by registering an electronic device with a server, activating a promotional offer stored on the server, receiving location information of the electronic device by the server over a network, determining the electronic device is to receive the promotional offer based upon the received location information, sending the promotional offer from the server to the electronic device over the network, sending a positive response to the promotional offer from the electronic device, over the network, and to the server, and sending a confirmation of the positive response from the server, over the network, and to the electronic device.

Abstract translation: 一种用于通过向服务器注册电子设备来传送促销优惠的方法和系统，激活存储在服务器上的促销优惠，由服务器通过网络接收电子设备的位置信息，确定电子设备是接收促销优惠 基于所接收的位置信息，通过网络将促销优惠从服务器发送到电子设备，通过网络向服务器发送对电子设备的促销优惠的肯定响应，并且发送确认 从服务器，网络和电子设备的积极响应。

公开(公告)号：WO2007120501A3

公开(公告)日：2007-10-25

申请号：PCT/US2007/008139

申请日：2007-04-03

Applicant: LEOTEK ELECTRONICS CORPORATION ,  WU, Chen-ho ,  TU, Chin-Wang

Inventor： WU, Chen-ho ,  TU, Chin-Wang

IPC: H01J13/46

Abstract: A method and device for replacing a fluorescent tube lamp with an LED lamp. The LED lamp includes an elongated electrical assembly having ends terminating in first and second electrical connectors, and a plurality of LEDs mounted to the elongated electrical assembly. Mounting adaptors connect with the first and second electrical connectors, and have protruding pins to connect with conventional lamp socket connectors. The mounting adaptors have rotating connectors for connecting with the first and second electrical connectors of the LED lamp, so that the LED lamp orientation can be rotated after the LED lamp is fully mounted to the lamp socket connectors.

公开(公告)号：WO2007106521A2

公开(公告)日：2007-09-20

申请号：PCT/US2007/006402

申请日：2007-03-13

Applicant: OPTIMEDICA CORPORATION ,  BELL, Katrina ,  SIMONEAU, Michael ,  MORDAUNT, David

Inventor： BELL, Katrina ,  SIMONEAU, Michael ,  MORDAUNT, David

IPC: A61B5/00

CPC classification number: A61F9/00821 ,  A61B90/00 ,  A61B2560/045

Abstract: A medical system that includes a medical device having a computing unit for controlling the medical device to perform a clinical procedure, a secondary computing device linked to the medical device via a first communications link, and an external resource or network linked to the secondary computing device via a second communications link. The secondary computing device is configured to provide a communications interface between the medical device and the external resource or network. The secondary computing device can include an input/output unit to access data stored on the medical device and/or the secondary computing device, and to input data relating to the clinical procedure performed by the medical device.

Abstract translation: 一种医疗系统，其包括具有用于控制医疗装置执行临床过程的计算单元的医疗装置，经由第一通信链路与医疗装置连接的辅助计算装置，以及链接到辅助计算装置的外部资源或网络 通过第二通信链路。 辅助计算设备被配置为提供医疗设备和外部资源或网络之间的通信接口。 辅助计算设备可以包括用于访问存储在医疗设备和/或辅助计算设备上的数据的输入/输出单元，以及输入与由医疗设备执行的临床过程有关的数据。

公开(公告)号：WO2007100615A3

公开(公告)日：2007-09-07

申请号：PCT/US2007/004635

申请日：2007-02-21

Applicant: ARIST INSTRUMENTS, INC. ,  ROSENCWAIG, Allan ,  WILLENBORG, David ,  CHEN, Li

Inventor： ROSENCWAIG, Allan ,  WILLENBORG, David ,  CHEN, Li

IPC: G01N21/00

Abstract: An inspection system and method for inspecting a sample surface, with a light source for generating a probe beam of light, a high NA lens for focusing the probe beam onto a sample surface, and collecting a scattered probe beam from the sample surface, optics for imaging the scattered probe beam onto a detector having a plurality of detector elements that generate output signals in response to the scattered probe beam, and a processor for analyzing the output signals to identify defects on the sample surface. Shaping the beam into a stripe shape increases intensity without sacrificing throughput. Offsetting the beam from the center of the high NA lens provides higher angle illumination. Crossed polarizers also improve signal quality. A homodyne or heterodyne reference beam (possibly using a frequency altering optical element) can be used to create an interferometric signal at the detector for improved signal to noise ratios.