公开(公告)号：WO2018194548A1

公开(公告)日：2018-10-25

申请号：PCT/US2017/027949

申请日：2017-04-17

Applicant: INTEL CORPORATION

Inventor： NIKONOV, Dmitri, E. ,  MANIPATRUNI, Sasikanth ,  YOUNG, Ian, A.

IPC: G01R33/12

CPC classification number: G01R33/12 ,  G01R33/0385 ,  G01R33/093

Abstract: Embodiments are generally directed to sensing of magnetic domains in magnetic materials. An embodiment of an apparatus includes a measurement head to sense magnetism of a magnetic material; and one or more spin valves, the one or more spin valves being contained in the measurement head. The one or more spin valves are to provide for sensing of magnetism of the magnetic material in multiple directions.

公开(公告)号：WO2018182740A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025604

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： MANIPATRUNI, Sasikanth ,  NIKONOV, Dmitri, E. ,  YOUNG, Ian, A.

IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/222 ,  H01L43/06 ,  H03K19/18

Abstract: Techniques are disclosed for forming magnetic random access memory (MRAM) devices and logic devices that includes a layer of material to induce a spin Hall effect (SHE) that is in contact with a layer of a spin absorption material. Disposing a spin absorption material layer in contact with a SHE material improves switching efficiency of devices that include this interface.

公开(公告)号：WO2017155511A1

公开(公告)日：2017-09-14

申请号：PCT/US2016/021262

申请日：2016-03-07

Applicant: INTEL CORPORATION

Inventor： NIKONOV, Dmitri, E. ,  MANIPATRUNI, Sasikanth ,  YOUNG, Ian, A.

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/10 ,  H01L43/00 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a first ferromagnet (FM) layer having a first end and a second end; a spin-orbit-coupling (SOC) layer adjacent to the first FM layer near the first end; and an inverse SOC (ISOC) layer adjacent to the first FM layer near the second end. Described is a system which comprises: a memory; a processor coupled to the memory, the processor having a spin wave device, which comprises an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to communicate with another device.

Abstract translation: 描述了一种设备，其包括：具有第一端和第二端的第一铁磁体（FM）层; 在第一端附近与第一FM层相邻的自旋 - 轨道耦合（SoC）层; 以及在第二端附近与第一FM层相邻的逆SOC（ISOC）层。 描述的系统包括：存储器; 耦合到所述存储器的处理器，所述处理器具有自旋波器件，所述自旋波器件包括根据上述装置的装置; 以及一个允许处理器与另一个设备通信的无线接口。

公开(公告)号：WO2017111876A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000511

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： MORRIS, Daniel, H. ,  AVCI, Uygar, E. ,  YOUNG, Ian, A.

IPC: H01L21/768 ,  G06F15/78

CPC classification number: H01L23/53209 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528

Abstract: Described is an apparatus which comprises: a first interconnect; a second interconnect; a third interconnect; a first via comprising a metal-insulator-transition (MIT) material, the first via to couple the first interconnect to the third interconnect; and a second via comprising the MIT material, the second via to couple the second interconnect to the third interconnect.

Abstract translation: 描述了一种设备，其包括：第一互连; 第二互连; 第三互连; 包括金属 - 绝缘体 - 过渡（MIT）材料的第一通孔，将所述第一互连耦合到所述第三互连的所述第一通孔; 以及包括MIT材料的第二通孔，将第二互连耦合到第三互连的第二通孔。

公开(公告)号：WO2014209332A1

公开(公告)日：2014-12-31

申请号：PCT/US2013/048351

申请日：2013-06-27

Applicant: INTEL CORPORATION

Inventor： AVCI, Uygar, E. ,  KIM, Raseong ,  YOUNG, Ian, A.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66977 ,  H01L29/7391

Abstract: Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region formed above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around regions.

Abstract translation: 描述了具有未掺杂漏极覆盖环绕区域的隧穿场效应晶体管（TFET）。 例如，隧道场效应晶体管（TFET）包括形成在衬底上方的均质有源区。 同质结有源区包括掺杂源极区，未掺杂沟道区，缠绕区和掺杂漏极区。 在未掺杂的沟道区域，源极和缠绕区域之间形成栅电极和栅介电层。

公开(公告)号：WO2014081525A1

公开(公告)日：2014-05-30

申请号：PCT/US2013/066452

申请日：2013-10-23

Applicant: INTEL CORPORATION

Inventor： MANIPATRUNI, Sasikanth ,  NIKONOV, Dmitri, E. ,  YOUNG, Ian, A.

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: Described are apparatus and method for simulating spintronic integrated circuit (SPINIC), the method comprising: generating a spin netlist indicating connections of spin nodes of spin circuits and nodes of general circuits; and modifying a modified nodal analysis (MNA) matrix for general circuits to generate a spin MNA matrix for solving spin circuits and general circuits of the spin netlist.

Abstract translation: 描述了用于模拟自旋电子集成电路（SPINIC）的装置和方法，所述方法包括：产生指示自旋电路的自旋节点和通用电路节点的连接的自旋网表; 并修改用于通用电路的修改的节点分析（MNA）矩阵以产生用于求解自旋网络的自旋电路和一般电路的自旋MNA矩阵。