公开(公告)号：WO2005062658A1

公开(公告)日：2005-07-07

申请号：PCT/US2004/038984

申请日：2004-11-19

Applicant: INTEL CORPORATION (a Corporation of Delaware) ,  STEPHENS, Adrian

Inventor： STEPHENS, Adrian

IPC: H04Q7/38

CPC classification number: H04W36/26

Abstract: An apparatus and a system, as well as a method and article, may operate to receive a request associated with a specification at a first access point, and to locate a second access point capable of supporting the specification. A handoff from the first access point to the second access point may be affected.

Abstract translation: 装置和系统以及方法和物品可以操作以在第一接入点处接收与规范相关联的请求，并且定位能够支持规范的第二接入点。 从第一接入点到第二接入点的切换可能受到影响。

公开(公告)号：WO2005062491A1

公开(公告)日：2005-07-07

申请号：PCT/US2004/039483

申请日：2004-11-24

Applicant: INTEL CORPORATION (a Corporation of Delaware) ,  TSIEN, Chih ,  LIU, Jiewen

Inventor： TSIEN, Chih ,  LIU, Jiewen

IPC: H04B7/005

CPC classification number: H04W52/243 ,  H04W24/00 ,  H04W52/10 ,  H04W52/50 ,  H04W84/12

Abstract: A communication station performs closed-loop transmit power control and adjusts its transmit power level based on an access pint sensitivity, a path loss and/or link margin variation. An average received power level of orthogonal frequency-division multiplexed (OFDM) subcarriers of an OFDM channel may be measured at the communication station, and the path loss may be estimated from an access point transmit power level and the measured power level. The communication station may request an access point’s transmit power level and link margin from the access point prior to estimating the path loss. The communication station may calculate the access point sensitivity by subtracting path loss and the access point link margin from the communication station’s transmit power level. The link margin variation may be estimated from an access point transmit power variation, an indoor path loss variation, and/or a receiver power measurement error of the communication station.

Abstract translation: 通信站执行闭环发射功率控制，并且基于接入品脱灵敏度，路径损耗和/或链路容限变化来调整其发射功率电平。 可以在通信站处测量OFDM信道的正交频分复用（OFDM）子载波的平均接收功率电平，并且可以从接入点发射功率电平和所测量的功率电平估计路径损耗。 在估计路径损耗之前，通信站可以从接入点请求接入点的发射功率电平和链路余量。 通信站可以通过从通信站的发射功率电平减去路径损耗和接入点链路余量来计算接入点灵敏度。 可以从通信站的接入点发射功率变化，室内路径损耗变化和/或接收机功率测量误差估计链路余量变化。

公开(公告)号：WO2005020480A1

公开(公告)日：2005-03-03

申请号：PCT/US2004/026258

申请日：2004-08-13

Applicant: INTEL CORPORATION (a Corporation of Delaware)

Inventor： SEETHARAMAN, Shivakumar ,  KIZILOHLU, Kursad

IPC: H04B10/158

CPC classification number: H03F3/45183 ,  H03F1/08 ,  H03F3/082 ,  H04B10/693

Abstract: Described is an apparatus comprising a transimpedance amplifier to receive an input current from a photodiode and provide an output voltage at first and second differential output terminals. A receive signal strength indicator may generate a differential receive signal strength indication (RSSI) signal based, at least in part, upon a voltage across the first and second differential output terminals.

Abstract translation: 描述了一种包括跨阻放大器的装置，用于接收来自光电二极管的输入电流并在第一和第二差分输出端提供输出电压。 接收信号强度指示器可以至少部分地基于第一和第二差分输出端子两端的电压产生差分接收信号强度指示（RSSI）信号。

公开(公告)号：WO2004095283A2

公开(公告)日：2004-11-04

申请号：PCT/US2004/004092

申请日：2004-02-11

Applicant: INTEL CORPORATION (a corporation of Delaware)

Inventor： LEVIT-GUREVICH, Konstantin ,  LIOKUMOVICH, Igor ,  SHAMIR, Ido

IPC: G06F11/36

CPC classification number: G06F9/45537

Abstract: According to one embodiment, a computer system is disclosed. The computer system comprises a central processing unit (CPU) to generate and control a virtual machine that runs simulated instruction code and create an abstraction of a real machine so that operation of a real operating system for the computer system is not impeded.

Abstract translation: 根据一个实施例，公开了一种计算机系统。 计算机系统包括中央处理单元（CPU），用于生成和控制运行模拟指令代码并创建真实机器抽象的虚拟机，从而不妨碍对计算机系统的真实操作系统的操作。

公开(公告)号：WO2003017006A2

公开(公告)日：2003-02-27

申请号：PCT/US2002/023090

申请日：2002-07-18

Applicant: INTEL CORPORATION (a corporation of Delaware)

Inventor： AMINZADEH, Mehran ,  FAHY, Michael

IPC: G03F7/20

CPC classification number: G03F9/7026 ,  G03F7/70425 ,  G03F9/7023

Abstract: A method is described for improving the exposure focus for modern steppers used in the lithography of semiconductor substrates such as wafers. A wafer is sawed from a semiconductor ingot in a particular direction relative to a reference point on the ingot. As a result of the sawing, a series of raised and recessed formations manifest on the surface of the wafer. After various layers have been added to the wafer and the photoresist layer is ready to be removed, the wafer is aligned with the stepper so that a dynamic focus area of the stepper is aligned with the formations and/or the sawing direction. Such alignment improves the critical dimension control and reduces variability in printing small geometry features during lithography, resulting in higher yields.

Abstract translation: 描述了一种用于改善在诸如晶片的半导体衬底的光刻中使用的现代步进器的曝光焦点的方法。 相对于锭上的参考点，从半导体锭沿特定方向锯切晶片。 作为锯切的结果，在晶片的表面上表现出一系列凸起和凹陷的结构。 在将各种层已经添加到晶片并且光致抗蚀剂层准备被去除之后，晶片与步进器对准，使得步进器的动态聚焦区域与地层和/或锯切方向对准。 这种对准改进了临界尺寸控制，并且减小了在光刻期间打印小几何特征的可变性，导致更高的产量。

公开(公告)号：WO2014019127A1

公开(公告)日：2014-02-06

申请号：PCT/CN2012/079394

申请日：2012-07-31

Applicant: INTEL CORPORATION (a corporation of Delaware)

Inventor： SHU, Kangyuan ,  DING, Junyong ,  LE, Yongnian ,  LIN, Weiliang, Lion ,  DENG, Xuefeng ,  YAN, Yaojie

IPC: G06T1/00

CPC classification number: G06T1/20 ,  G06F9/5011 ,  G06F9/5044 ,  G06T1/60

Abstract: Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.

Abstract translation: 本文通常描述用于混合计算机系统中的增强图形呈现性能的系统和方法的实施例。 在一些实施例中，将通过网络浏览器呈现给用户的框架，应用程序或网页中的图形元素由第一处理器或第二处理器基于第一或第二处理器 第二处理器配备或配置为提供更快的渲染。 渲染引擎可以基于历史或预期的渲染性能来利用任一处理器，并且可以在硬件解码器和通用处理器之间动态切换以实现渲染时间性能改进。 处理器之间的切换可能被限制为固定数量的开关或开关频率。

公开(公告)号：WO2014004012A2

公开(公告)日：2014-01-03

申请号：PCT/US2013/044363

申请日：2013-06-05

Applicant: INTEL CORPORATION (a corporation of Delaware)

Inventor： HAFEZ, Walid M. ,  YEH, Jeng-Ya D. ,  TSAI, Curtis ,  PARK, Joodong ,  JAN, Chia-Hong ,  BHIMARASETTI, Gopinath

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

Abstract translation: 描述了具有电介质衬里的高电压三维器件和形成具有电介质衬里的高电压三维器件的方法。 例如，半导体结构包括设置在衬底上的第一鳍状有源区和第二鳍状有源区。 第一栅极结构设置在第一鳍状件有源区的顶表面上方并且沿着第一鳍状件有源区的侧壁。 第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。 第一栅极电介质由布置在第一鳍状有源区上并且沿着第一隔离物的侧壁的第一电介质层以及布置在第一电介质层上并且沿着第一隔离物的侧壁布置的不同的第二电介质层组成。 该半导体结构还包括第二栅极结构，该第二栅极结构设置在第二鳍状有源区的顶表面上方并且沿着第二鳍状有源区的侧壁。 第二栅极结构包括第二栅极电介质，第二栅极电极和第二间隔物。 第二栅极电介质由设置在第二鳍状有源区上并且沿着第二隔离物的侧壁的第二电介质层构成。

公开(公告)号：WO2013137710A1

公开(公告)日：2013-09-19

申请号：PCT/MY2012/000055

申请日：2012-03-13

Applicant: INTEL CORPORATION (a corporation of Delaware) ,  LOO, Howe Yin ,  CHEE, Choong Kooi

Inventor： LOO, Howe Yin ,  CHEE, Choong Kooi

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H05K1/181 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/427 ,  H01L23/49827 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H05K1/141 ,  H05K1/144 ,  H05K3/30 ,  H05K3/3415 ,  H05K2201/10378 ,  Y10T29/4913

Abstract: The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.

Abstract translation: 本说明书涉及制造微电子结构的领域。 微电子结构可以包括具有开口的微电子衬底，其中开口可以通过微电子衬底形成，或者可以是在微电子衬底中形成的凹部。 微电子封装可以附接到微电子衬底，其中微电子封装可以包括具有第一表面和相对的第二表面的插入件。 微电子器件可以附接到插入器第一表面，并且插入器可以通过插入器第一表面附接到微电子衬底，使得微电子器件延伸到开口中。 至少一个次级微电子器件可以附接到插入件第二表面。

公开(公告)号：WO2012083484A1

公开(公告)日：2012-06-28

申请号：PCT/CN2010/002104

申请日：2010-12-21

Applicant: INTEL CORPORATION (a corporation of Delaware) ,  LI, Haitao ,  CHEN, Yang, Young

Inventor： LI, Haitao ,  CHEN, Yang, Young

IPC: G06F1/16

CPC classification number: G06F1/1632

Abstract: A hot-pluggable docking station may include one or more central processing units (CPUs) and internal memory and other supporting circuitry within the dock. When a lower performance device is docked it may utilize this additional computing power as well as any of the peripherals connected to the dock thus enhancing the computing abilities of the lower performance device. In addition, the smart docking station may be networked or otherwise connected to other such smart docks each acting as a node in a distributed computing network and their computing ability may be available and shared with the network.

Abstract translation: 热插拔对接站可以包括一个或多个中央处理单元（CPU）和内部存储器以及坞内的其他支持电路。 当较低性能的设备被对接时，它可以利用这种额外的计算能力以及连接到坞站的任何外围设备，从而增强了较低性能设备的计算能力。 此外，智能对接站可以联网或以其他方式连接到其他这样的智能坞站，每个智能坞站充当分布式计算网络中的节点，并且其计算能力可以与网络可用和共享。

公开(公告)号：WO2006004981A1

公开(公告)日：2006-01-12

申请号：PCT/US2005/023425

申请日：2005-06-29

Applicant: INTEL CORPORATION (a corporation of Delaware) ,  MESMER, Ralph, M. ,  LEE, Ken, K. ,  BOOTH, Lawrence, A., Jr.

Inventor： MESMER, Ralph, M. ,  LEE, Ken, K. ,  BOOTH, Lawrence, A., Jr.

IPC: G09G3/36

CPC classification number: H04N1/00129 ,  H04N1/00127 ,  H04N1/028 ,  H04N1/02805 ,  H04N2201/0081

Abstract: Methods and apparatus to scan an object with a color display are disclosed. In one aspect, an apparatus may include a driver to control sub-pixels of a color display, and logic of the driver to cause a first sub-pixel of the color display to emit light and a second sub-pixel of the color display to detect light.

Abstract translation: 公开了用彩色显示器扫描对象的方法和装置。 在一个方面，一种装置可以包括用于控制彩色显示器的子像素的驱动器，以及驱动器的逻辑，以使彩色显示器的第一子像素发光，并将彩色显示器的第二子像素发送到 检测光。