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    MODULAR LIGHT-EMITTING PANEL ASSEMBLY
    32.
    发明申请
    MODULAR LIGHT-EMITTING PANEL ASSEMBLY 审中-公开
    模块化发光面板组件

    公开(公告)号：WO2013058961A1

    公开(公告)日：2013-04-25

    申请号：PCT/US2012/057837

    申请日：2012-09-28

    Applicant: RAMBUS INC.

    Inventor： MCCOLLUM, Timothy A. ,  PARKER, Jeffery R. ,  PODOJIL, Gregg M.

    IPC: F21V8/00 ,  F21V5/00

    CPC classification number: G02B6/0078 ,  F21V13/00 ,  G02B6/0075

    Abstract: A modular light-emitting panel assembly has first and second light guides edge lit by respective light sources. Each light guide has a light input edge, opposed side edges, opposed major surfaces and a pattern of light extracting elements at at least one of the major surfaces. The light guides are juxtaposed with a side edge of the first light guide abutting a side edge of the second light guide at a seam and with the major surfaces nominally coplanar. Various embodiments of the panel assembly additionally include respective structures that reduce visibility of the seam when the light sources illuminate the panel assembly.

    Abstract translation: 模块化发光面板组件具有由相应光源照亮的第一和第二光导。 每个光导具有光输入边缘，相对的侧边缘，相对的主表面和在至少一个主表面处的光提取元件的图案。 导光体与第一导光体的侧边缘并列，与第二导光体的边缘接合，并且主表面名义上共面。 面板组件的各种实施例另外包括当光源照亮面板组件时降低接缝的可视性的相应结构。

    LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER
    33.
    发明申请
    LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER 审中-公开
    低延迟，频率敏捷的时钟倍频器

    公开(公告)号：WO2013006231A3

    公开(公告)日：2013-04-04

    申请号：PCT/US2012039268

    申请日：2012-05-24

    Applicant: RAMBUS INC ,  ZERBE JARED L ,  LEIBOWITZ BRIAN S ,  HOSSAIN MASUM

    Inventor： ZERBE JARED L ,  LEIBOWITZ BRIAN S ,  HOSSAIN MASUM

    IPC: H03K5/00 ,  H03B19/00

    CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally- staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

    Abstract translation: 在第一时钟倍频器中，并行操作具有光谱交错锁定范围的多个注入锁定振荡器（ILO），以实现比单独ILO的集中输入频率范围宽得多的集中输入频率范围。 在每个输入频率改变之后，可以根据一个或多个合格标准评估ILO输出时钟，以选择ILO中的一个作为最终时钟源。 在第二个时钟倍频器中，柔性注入速率注入锁定振荡器锁定超级谐波，次谐波或频率注入脉冲，在不同的注入脉冲速率之间无缝切换，以实现宽泛的输入频率范围。 由第一和/或第二时钟倍频器响应于输入时钟而实现的倍频因子被实时确定，然后与编程的（期望的）倍增因子进行比较以在倍频的不同分频实例之间进行选择 时钟。

    DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS
    34.
    发明申请
    DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS 审中-公开
    通过选择性地启用和禁用数据链接动态更改数据访问带宽

    公开(公告)号：WO2013009442A3

    公开(公告)日：2013-03-14

    申请号：PCT/US2012043258

    申请日：2012-06-20

    Applicant: RAMBUS INC ,  WARE FREDERICK A

    Inventor： WARE FREDERICK A

    IPC: G06F13/14 ,  G06F13/16 ,  G06F13/38

    CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F1/3293 ,  G06F13/1694 ,  Y02D10/151 ,  Y02D10/157

    Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

    Abstract translation: 设备间信息传输的带宽会动态改变，以适应系统中采用的功率模式之间的转换。 通过选择性地启用和禁用携带信息的单独控制链路和数据链路来改变带宽。 在系统的最高带宽模式期间，所有的数据和控制链路都能够在整个过程中提供最大的信息。 在系统的一个或多个较低带宽模式期间，禁用至少一个数据链路和/或至少一个控制链路以降低设备的功耗。 在每个低带宽模式期间保持启用至少一个数据链路和至少一个控制链路。 对于这些链路，相同的信令速率用于两种带宽模式，以减少否则将由信令速率改变引起的延迟。 此外，还会为禁用的链接生成校准信息，以便这些链接可以快速重新投入使用。

    SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS ON RRAM CELLS
    37.
    发明申请
    SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS ON RRAM CELLS 审中-公开
    在RRAM电池上执行存储器操作的系统和方法

    公开(公告)号：WO2013028377A1

    公开(公告)日：2013-02-28

    申请号：PCT/US2012/050368

    申请日：2012-08-10

    Applicant: RAMBUS INC. ,  HAUKNESS, Brent, Steven

    Inventor： HAUKNESS, Brent, Steven

    IPC: G11C13/00 ,  G11C16/06

    CPC classification number: G11C13/0026 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0088 ,  G11C2213/79

    Abstract: A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.

    Abstract translation: 电阻RAM（RRAM）器件具有位线，字线，承载基本静态和非负电压的偏置电压的源极线，RRAM单元和耦合到位线电路的位线控制。 RRAM单元包括耦合到字线的栅极节点，耦合到源极线的偏置节点和耦合到位线的位线节点。 位线控制电路被配置为产生非负指令电压，以对RRAM单元执行相应的存储器操作。

    CALIBRATING A RETRO-DIRECTIVE ARRAY FOR AN ASYMMETRIC WIRELESS LINK
    38.
    发明申请
    CALIBRATING A RETRO-DIRECTIVE ARRAY FOR AN ASYMMETRIC WIRELESS LINK 审中-公开
    为非对称无线链路校准一个重定向阵列

    公开(公告)号：WO2013028296A1

    公开(公告)日：2013-02-28

    申请号：PCT/US2012/047751

    申请日：2012-07-20

    Applicant: RAMBUS INC. ,  ARYANFAR, Farshid ,  REN, Jihong

    Inventor： ARYANFAR, Farshid ,  REN, Jihong

    IPC: H04B7/04 ,  H01Q3/26

    CPC classification number: H01Q1/50 ,  H01Q1/241 ,  H01Q3/2647 ,  H01Q3/267 ,  H04B17/12 ,  H04B17/13 ,  H04B17/14

    Abstract: The disclosed embodiments relate to a technique for calibrating a retro-directive array. During the calibration process, the system measures a gain g 1 through a first pair of antennas in the retro-directive array. Next, the system measures a gain g 2 through a second pair of antennas in the retro-directive array. The system then simultaneously measures a combined gain G 1 , 2 through the first and second pairs of antennas in the retro-directive array. If G 1 , 2 is less than g 1 + g 2 by more than a threshold value, the system calibrates a phase relationship between the first and second pairs of antennas.

    Abstract translation: 所公开的实施例涉及用于校准后向指令阵列的技术。 在校准过程中，系统通过反向指令阵列中的第一对天线测量增益g1。 接下来，系统通过后向指令阵列中的第二对天线测量增益g2。 然后，该系统同时测量通过后向指令阵列中的第一和第二对天线的组合增益G1.2。 如果G1,2小于g1 + g2超过阈值，则系统校准第一和第二对天线之间的相位关系。

    LIGHT BULB WITH THERMAL FEATURES
    39.
    发明申请
    LIGHT BULB WITH THERMAL FEATURES 审中-公开
    具有热特性的灯泡

    公开(公告)号：WO2013023023A2

    公开(公告)日：2013-02-14

    申请号：PCT/US2012/050080

    申请日：2012-08-09

    Applicant: RAMBUS INC. ,  PETROSKI, James T. ,  BAUER, Witold ,  PARKER, Jeffery R.

    Inventor： PETROSKI, James T. ,  BAUER, Witold ,  PARKER, Jeffery R.

    IPC: F21V8/00 ,  F21V29/00

    CPC classification number: F21K9/61 ,  F21K9/23 ,  F21V29/70 ,  F21V29/773 ,  G02B6/0031 ,  G02B6/0085 ,  Y02B20/19

    Abstract: A light bulb includes a light guide, light source, and housing. The light guide is configured as an open-ended hollow body surrounding an internal volume and defining a longitudinal axis. The light guide has inner and outer major surfaces. The light source is configured to edge light the light guide. The housing is at one end of the light guide. In one embodiment, fins extend from the housing adjacent the outer major surface, each fin separated from the outer major surface by an air gap to allow air flow between the fin and outer major surface. In another embodiment, a heat sink is disposed in the internal volume and configured as a hollow body with a branched cross section. Each branch extends outward from a common center and defines an air flow channel that terminates in an orifice aligned with a respective through-slot of the light guide.

    Abstract translation: 灯泡包括光导，光源和外壳。 光导被构造为围绕内部体积并限定纵向轴线的开放式中空体。 光导具有内外主表面。 光源被配置为边缘照亮光导。 外壳位于光导的一端。 在一个实施例中，翅片从邻近外主表面的壳体延伸，每个翅片与外主表面间隔开一气隙，以允许空气在翅片和外主表面之间流动。 在另一个实施例中，散热器设置在内部容积中，并且构造成具有分支横截面的中空体。 每个分支从公共中心向外延伸，并且限定一个气流通道，其终止于与导光体的相应通孔对准的孔中。

    SUPPORTING CALIBRATION FOR SUB-RATE OPERATION IN CLOCKED MEMORY SYSTEMS
    40.
    发明申请
    SUPPORTING CALIBRATION FOR SUB-RATE OPERATION IN CLOCKED MEMORY SYSTEMS 审中-公开
    支持在时钟记忆系统中进行子频率运算的校准

    公开(公告)号：WO2012154507A1

    公开(公告)日：2012-11-15

    申请号：PCT/US2012/036370

    申请日：2012-05-03

    Applicant: RAMBUS INC. ,  BANSAL, Akash ,  FRANS, Yohan U. ,  KASAMSETTY, Kishore V. ,  BYSTROM, Todd ,  LI, Simon ,  VAIDYANATH, Arun

    Inventor： BANSAL, Akash ,  FRANS, Yohan U. ,  KASAMSETTY, Kishore V. ,  BYSTROM, Todd ,  LI, Simon ,  VAIDYANATH, Arun

    IPC: G11C7/00 ,  G06F1/04

    CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

    Abstract translation: 公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中相应的数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2速率，1/4或1/8）相关联 频率）。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

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