公开(公告)号：WO2008131203A3

公开(公告)日：2009-06-04

申请号：PCT/US2008060793

申请日：2008-04-18

Applicant: QUALCOMM INC ,  ZHANG BO ,  JIAO GUOFANG ,  YUN JAY CHUNSUP ,  DU YUN

Inventor： ZHANG BO ,  JIAO GUOFANG ,  YUN JAY CHUNSUP ,  DU YUN

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/355

CPC classification number: G06F9/345 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/342 ,  G06F9/3877

Abstract: A computer addressing mode and memory access method rely on a memory segment identifier and a memory segment mask for indicating memory locations. In this addressing mode, a processor receives an instruction comprising the memory segment identifier and memory segment mask. The processor employs a two-level address decoding scheme to access individual memory locations. Under this decoding scheme, the processor decodes the memory segment identifier to select a particular memory segment. Each memory segment includes a predefined number of memory locations. The processor selects memory locations within the memory segment based on mask bits set in the memory segment mask. The disclosed addressing mode is advantageous because it allows non-consecutive memory locations to be efficiently accessed.

Abstract translation: 计算机寻址模式和存储器访问方法依赖于存储器段标识符和用于指示存储器位置的存储器段掩码。 在该寻址模式中，处理器接收包括存储器段标识符和存储器段掩码的指令。 处理器采用两级地址解码方案来访问各个存储单元。 在该解码方案下，处理器解码存储器段标识符以选择特定存储器段。 每个存储器段包括预定义数量的存储器位置。 处理器基于在存储器段掩码中设置的掩码位来选择存储器段内的存储器位置。 所公开的寻址模式是有利的，因为它允许有效地访问非连续存储器位置。

公开(公告)号：WO2008036946A1

公开(公告)日：2008-03-27

申请号：PCT/US2007/079235

申请日：2007-09-21

Applicant: INTEL CORPORATION ,  KAPOOR, Rajiv ,  ZOHAR, Ronen ,  BUXTON, Mark ,  GOTTLIEB, Koby ,  SPERBER, Zeev

Inventor： KAPOOR, Rajiv ,  ZOHAR, Ronen ,  BUXTON, Mark ,  GOTTLIEB, Koby ,  SPERBER, Zeev

IPC: G06F9/22 ,  G06F9/305 ,  G06F7/02 ,  G06F7/06

CPC classification number: G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on the first and second data. The logical comparisons may be performed on each bit of the first and second data, or may be performed only on certain bits. For at least one embodiment, at least the first data includes packed data elements, and the logical comparisons are performed on the most significant bits of the packed data elements. The logical comparisons may include comparison of the same respective bits of the first and second data, and also includes logical comparisons of bits of the first data with the complement of the corresponding bits of the second data. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting one or more flags, which in turn may be utilized by a branching unit. Alternatively, the branch support actions may include branching to an indicated target code location.

Abstract translation: 一种用于在处理器中包括用于对打包或未打包的数据执行逻辑比较和分支支持操作的指令的方法和装置。 在一个实施例中，处理器耦合到存储器。 存储器中存储有第一数据和第二数据。 处理器对第一和第二数据执行逻辑比较。 可以对第一和第二数据的每个比特执行逻辑比较，或者可以仅对某些比特执行逻辑比较。 对于至少一个实施例，至少第一数据包括打包数据元素，并且对打包数据元素的最高有效位执行逻辑比较。 逻辑比较可以包括第一和第二数据的相同各个比特的比较，并且还包括第一数据的比特与第二数据的相应比特的补码的逻辑比较。 基于这些比较，采取分支支持行动。 这种分支支持动作可以包括设置一个或多个标志，其又可以由分支单元使用。 或者，分支支持动作可以包括分支到指示的目标代码位置。

公开(公告)号：WO2004053841A3

公开(公告)日：2004-10-28

申请号：PCT/US0336764

申请日：2003-11-17

Applicant: GEMTECH SYSTEMS LLC ,  NAIR GOPALAN N ,  NAIR GOURI

Inventor： NAIR GOPALAN N ,  NAIR GOURI

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/345 ,  G06F9/38 ,  G06F15/00 ,  G06F17/16 ,  G11B20060101

CPC classification number: G06F9/30098 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3879 ,  G06F9/3887

Abstract: A matrix data processor is implemented wherein data elements are stored in physical registers (720). After being stored in the physical registers, the data elements are then treated as matrix elements (730 and 740). Matrix operations are then performed on the elements to generate results (750), which are stored (770) in an identified (760) destination matrix.

Abstract translation: 实现矩阵数据处理器，其中数据元素存储在物理寄存器（720）中。 在存储在物理寄存器中之后，将数据元素作为矩阵元素（730和740）处理。 然后对元素执行矩阵运算以生成结果（750），其被存储（770）在识别的（760）目的地矩阵中。

公开(公告)号：WO2004042559A2

公开(公告)日：2004-05-21

申请号：PCT/EP0310597

申请日：2003-09-23

Applicant: INFINEON TECHNOLOGIES ,  DIRSCHERL GERD ,  GAMMEL BERNDT ,  SMOLA MICHAEL

Inventor： DIRSCHERL GERD ,  GAMMEL BERNDT ,  SMOLA MICHAEL

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/40 ,  G06F9/42 ,  G11C8/00

CPC classification number: G11C8/00 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/4425

Abstract: A processor (10) for processing a progam (26) with commands, comprising a mother program with a sub-program branch instruction (28) and a sub-program which is embodied in response to said sub-program branch instruction (28). The processor comprises a command processing device which, when the sub-program branch information (28) occurs inside the mother program, is configured in such a way that security information on the data required according to the processing of the sub-program in the mother program can be extracted from the sub-program branch instruction (28), the data required according to the processing of the sub-program in the mother program can be secured on the basis of said security information, a target address referring to the sub-program can be extracted from the sub-program branch information and, on the basis of the target address, the processing of the program can be continued with the sub-program.

Abstract translation: 一种用于执行程序（26）的命令，其包括与子程序跳转指令（28），并且响应于该子程序跳转命令（28）时要执行的子程序的母程序处理器（10）进行说明。 该处理器包括一个指令处理装置，其当在母程序从处理所述子节目数据之后固定在所述母程序所需信息的子节目跳跃命令（28）提取该子程序跳转指令（28）的发生而形成的基础上，处理后的备份信息 在提取从该指子程序子程序跳跃命令的目的地址所需要的母程序数据固定子程序，以使该程序的执行被继续与子程序的目的地址的基础上。

公开(公告)号：WO2003025737A1

公开(公告)日：2003-03-27

申请号：PCT/JP2002/008681

申请日：2002-08-28

Applicant: 株式会社エヌティーアイ ,  中村 貴利 ,  横田 昭寛

Inventor： 中村 貴利 ,  横田 昭寛

IPC: G06F7/00

CPC classification number: G06F9/30098 ,  G06F9/3001

Abstract: An operation apparatus for performing a series of operations for an input and outputting the result. The apparatus can perform operation at a high speed and flexibly. The apparatus has a plurality of operation units for selecting a predetermined input from a plurality of inputs, performing a predetermined operation, and outputting the result. The output of each operation unit is used as one of the inputs of another operation unit.

Abstract translation: 一种用于对输入进行一系列操作并输出结果的操作装置。 该装置可以高速且灵活地进行操作。 该装置具有多个操作单元，用于从多个输入中选择预定的输入，执行预定的操作并输出结果。 每个操作单元的输出用作另一个操作单元的输入之一。

公开(公告)号：WO2003019358A1

公开(公告)日：2003-03-06

申请号：PCT/US2002/027273

申请日：2002-08-27

Applicant: INTEL CORPORATION

Inventor： ROSENBLUTH, Mark ,  WOLRICH, Gilbert ,  BERNSTEIN, Debra

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/30098 ,  G06F9/30123 ,  G06F9/3851

Abstract: A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.

Abstract translation: 多线程处理器中基于配置信息分配资源的机制，该配置信息指示正在使用多少线程。

公开(公告)号：WO01086429A2

公开(公告)日：2001-11-15

申请号：PCT/US2001/014925

申请日：2001-05-08

IPC: G06F9/30

CPC classification number: G06F9/30101 ,  G06F9/30098

Abstract: An apparatus for reducing CPU latency by reducing CPU bus read/write cycles, the apparatus includes a hardware register capable of testing data for one or more validity bits. A CPU is in communication with the hardware register during a first bus cycle and the CPU directs the hardware register to drive the data substantially simultaneously to the CPU and a second register. The data validity signal is performed in close proximity to the data transfer to the CPU and the second hardware device and the validity signal is forwarded to the second register without a subsequent bus cycle instruction to the second register from the CPU.

Abstract translation: 一种通过减少CPU总线读/写周期来减少CPU等待时间的装置，该装置包括能够测试一个或多个有效位的数据的硬件寄存器。 CPU在第一个总线周期期间与硬件寄存器通信，CPU指示硬件寄存器将数据基本同时驱动到CPU和第二个寄存器。 在与CPU和第二硬件设备的数据传输非常接近的情况下执行数据有效信号，并且有效信号被转发到第二寄存器，而没有来自CPU的第二寄存器的后续总线周期指令。

公开(公告)号：WO01008005A1

公开(公告)日：2001-02-01

申请号：PCT/US2000/017630

申请日：2000-06-26

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318

CPC classification number: G06F9/3001 ,  G06F9/30032 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30141

Abstract: A processor has at least two sets of registers. The first set stores a matrix of data, and the second set stores a transposed copy of the matrix of data. When any portion of any row of the first set is modified, the corresponding portion of the column of the transposed copy in the second set is also automatically modified. A method of using two sets of registers for matrix processing by a processor includes storing a matrix of data into a first set of registers, the first set of registers having a first number of registers, each register comprising a first number of storage units, each storage unit storing an element of the matrix, and transposing the matrix of data into a second set of registers, the second set of registers having a second number of registers, each register comprising a second number of storage units. The method also includes referencing one of the first set of registers to operate on a row of the matrix of data, and referencing one of the second set of registers to operate on a column of the matrix of data.

Abstract translation: 处理器至少有两组寄存器。 第一组存储数据矩阵，第二组存储数据矩阵的转置副本。 当第一组的任何行的任何部分被修改时，第二组中转置副本的列的对应部分也被自动修改。 使用两组寄存器进行矩阵处理的方法包括将数据矩阵存储到第一组寄存器中，第一组寄存器具有第一数量的寄存器，每个寄存器包括第一数量的存储单元，每个寄存器包括第一数量的存储单元 存储单元存储矩阵的元素，以及将数据矩阵转置到第二组寄存器中，第二组寄存器具有第二数量的寄存器，每个寄存器包括第二数量的存储单元。 该方法还包括引用第一组寄存器中的一个来对数据矩阵的行进行操作，并且引用第二组寄存器中的一个来对数据矩阵的列进行操作。

公开(公告)号：WO00033177A1

公开(公告)日：2000-06-08

申请号：PCT/US1999/028609

申请日：1999-12-03

IPC: G06F9/30

CPC classification number: G06F9/3012 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30163 ,  G06F9/30167

Abstract: A processor executes an instruction set including instructions in which a register specifier is implicitly derived, based on another register specifier. One technique for implicitly deriving a register specifier is to add or substract one from a specifically-defined register specifier. Implicit derivation of a register specifier is selectively implemented for some opcodes. A decoder decodes instructions that use implicitly-derived register specifiers and reads the explicitly-defined register. The decoder generates pointers both to the explicitly-defined register and to the implicitly-derived register. In other embodiments, a pointer to registers within a register file includes an additional bit indicating that a register read is accompagnied by a read of an implicitly-derived register.

Abstract translation: 处理器基于另一个寄存器说明符执行指令集，该指令集包括其中隐含地导出寄存器说明符的指令。 用于隐式导出寄存器说明符的一种技术是从特定定义的寄存器说明符添加或减法。 一些操作码有选择地实现了寄存器说明符的隐式推导。 解码器解码使用隐式导出的寄存器说明符并读取明确定义的寄存器的指令。 解码器生成指向明确定义的寄存器和隐式导出寄存器的指针。 在其他实施例中，寄存器文件中的寄存器指针包括指示寄存器读取由隐式导出的寄存器的读取而被附加的附加位。

公开(公告)号：WO1993011490A1

公开(公告)日：1993-06-10

申请号：PCT/US1992008058

申请日：1992-09-21

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  HILTON, William, Kenneth ,  NOLAN, James, B. ,  POTTS, Walter, H.

IPC: G06F12/00

CPC classification number: G06F12/0623 ,  G06F9/30098 ,  G06F9/30138

Abstract: A hardware system provides a programmable method for addressing expanded memory specification (EMS) registers (20, 30) in a personal computing system functioning with an MS-Dos operating system or the like. The system provides hardware flexibility for addressing EMS registers at different addresses than the standard LIM EMS specification calls for, to permit utilization of register addresses in otherwise unavailable locations. The address translations are effected through hardware (Figure 5-all); so that no additional delays in the circuit operation occur.

Abstract translation: 硬件系统提供了一种用于在与MS-Dos操作系统等一起工作的个人计算系统中寻址扩展存储器规范（EMS）寄存器（20,30）的可编程方法。 该系统提供硬件灵活性，用于在不同于地址标准的LIM EMS规范要求的地址处寻址EMS寄存器，以允许在其他不可用位置使用寄存器地址。 地址转换通过硬件实现（图5全部）; 使得电路操作中不再发生额外的延迟。