公开(公告)号：WO2008016932A2

公开(公告)日：2008-02-07

申请号：PCT/US2007074883

申请日：2007-07-31

Applicant: SANDISK 3D LLC ,  FASOLI LUCA G ,  PETTI CHRISTOPHER J ,  SCHEUERLEIN ROY E

Inventor： FASOLI LUCA G ,  PETTI CHRISTOPHER J ,  SCHEUERLEIN ROY E

IPC: G11C11/00

CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C17/165

Abstract: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

Abstract translation: 描述了用于解码可编程和在一些实施例中的可重写无源元件存储器单元的示例性存储器阵列的电路和方法，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 另外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择选定阵列块内的一个或多个字线和位线，用于向选定阵列块内的选定存储器单元传送数据信息 并且用于将未选择的偏置条件传送给未选择的阵列块。

公开(公告)号：WO2007018661A3

公开(公告)日：2007-12-06

申请号：PCT/US2006018760

申请日：2006-05-12

Applicant: LATTICE SEMICONDUCTOR CORP

Inventor： DE LA CRUZ LOUIS ,  WHITE ALLEN ,  VERNENKER HEMANSHU

IPC: G11C8/00

CPC classification number: G11C8/10

Abstract: Systems and methods are disclosed herein to provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal. The registered address signal provides at least a true and a complement signal, with the true and complement signal set to approximately the same logical value upon assertion of the reset signal. An address pre-decoder, coupled to the address register, at least partially decodes the registered address signal to provide a pre-decoded output signal. A wordline driver, coupled to the address pre-decoder, receives a wordline enable signal and the pre-decoded output signal and provides a wordline signal based on the pre-decoded output signal upon assertion of the wordline enable signal.

Abstract translation: 本文公开了系统和方法，以提供用于存储器的改进的地址解码技术。 例如，根据本发明的实施例，集成电路包括接收复位信号的地址寄存器，时钟信号和地址信号，并提供注册的地址信号。 登记的地址信号提供至少一个真实和补码信号，在确认复位信号时，将真实和补码信号设置为近似相同的逻辑值。 耦合到地址寄存器的地址预解码器至少部分地解码注册的地址信号以提供预解码的输出信号。 耦合到地址预解码器的字线驱动器接收字线使能信号和预解码输出信号，并且在断言字线使能信号时，基于预解码的输出信号提供字线信号。

公开(公告)号：WO0146988A3

公开(公告)日：2007-08-23

申请号：PCT/US9930502

申请日：1999-12-21

Applicant: INTRINSITY INC ,  SENINGEN MICHAEL R ,  BLOMGREN JAMES S ,  POTTER TERENCE M

Inventor： SENINGEN MICHAEL R ,  BLOMGREN JAMES S ,  POTTER TERENCE M

IPC: G06F17/50 ,  G06F1/08 ,  G06F5/01 ,  G06F7/02 ,  G06F7/49 ,  G06F7/50 ,  G06F7/544 ,  G11C8/00 ,  G11C8/10 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419 ,  G11C11/56 ,  G11C19/00 ,  H03K19/00 ,  H03K19/003 ,  H03K19/08 ,  H03K19/096 ,  H03K19/21

CPC classification number: G06F1/08 ,  G06F5/015 ,  G06F7/02 ,  G06F7/026 ,  G06F7/483 ,  G06F7/49 ,  G06F7/508 ,  G06F7/5443 ,  G06F17/5045 ,  G06F2207/3824 ,  G11C7/1006 ,  G11C8/00 ,  G11C8/10 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419 ,  G11C11/56 ,  G11C19/00 ,  H03K19/0002 ,  H03K19/00346 ,  H03K19/00361 ,  H03K19/00384 ,  H03K19/0813 ,  H03K19/0963 ,  H03K19/215

Abstract: The present invention comprises a method and apparatus of routing a 1 of N signal to reduce the effective signal coupling between the signal wires. The present invention comprises a wire pack (129) with a plurality of wires for routing a 1 of N signal in a semiconductor device. While routing the wires of the wire pack (129), the present invention rotates the route of each individual wire to reduce the signal coupling between the wires. Additionally, an isolation barrier (132) borders the outside of the wire pack (149) to further reduce the signal coupling. The rotation of the wires allows each individual wire to be adjacent to each other wire for part of the wire's route. Other embodiments of the present invention include routing 1 of 3 signals and 1 of 4 signals.

Abstract translation: 本发明包括一种用于路由1个N信号以减少信号线之间的有效信号耦合的方法和装置。 本发明包括具有用于在半导体器件中路由1个N信号的多条导线的导线组件（129）。 在布线电线组件（129）的电线的同时，本发明旋转各个电线的路线，以减少电线之间的信号耦合。 此外，隔离屏障（132）与导线组件（149）的外部相接触，以进一步减小信号耦合。 电线的旋转允许每个单独的电线与电线的一部分路线相邻。 本发明的其它实施例包括路由1个3个信号和1个4个信号。

公开(公告)号：WO2007089802A2

公开(公告)日：2007-08-09

申请号：PCT/US2007002577

申请日：2007-01-30

Applicant: HEWLETT PACKARD DEVELOPMENT CO ,  ROBINETT WARREN ,  SNIDER GREGORY S ,  STEWART DUNCAN ,  STRAZNICKY JOSEPH

Inventor： ROBINETT WARREN ,  SNIDER GREGORY S ,  STEWART DUNCAN ,  STRAZNICKY JOSEPH

CPC classification number: G11C8/10 ,  G11C13/0023 ,  H03M13/51

Abstract: Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodimentof the present invention, an encoder-demulriplexer comprises a number of input signal lines and an encoder (1304) that generates an n-bit-constant-weight-code code-word internal address (1320, 1506, 1704) for each different input address (1318, 1702) received on the input signal lines. The encoder-demultiplexer also includes n microscale signal lines (1306-1311) on which an n-bit-constant-weight-code code word internal address is out put by the encoder and a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with then microscale signal lines (1306-1311) via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal adress (1320, 1506, 1704).

Abstract translation: 本发明的各种实施例涉及包括隧道电阻器纳米线结的解复用器，并且涉及用于在纳米级和混合尺度解复用器中可靠地寻址纳米线信号线的纳米线寻址方法。 在本发明的一个实施例中，编码器 - 解复用器包括多个输入信号线和编码器（1304），编码器（1304）为每个输入信号线生成n位恒定加权码字内部地址（1320,1506,1704） 在输入信号线上接收不同的输入地址（1318,1702）。 编码器 - 解复用器还包括n个微型信号线（1306-1311），编码器输出n位恒定加权码字内部地址，并且编码器 - 解复用器寻址的纳米线信号线互连 与经由隧道电阻器结的微米级信号线（1306-1311）相连，所述编码器 - 解复用器寻址的纳米线信号线均与n位恒定重量码码字内部地址（1320,1506,1704）相关联。

公开(公告)号：WO2007067832A2

公开(公告)日：2007-06-14

申请号：PCT/US2006/060417

申请日：2006-10-27

Applicant: FREESCALE SEMICONDUCTOR INC. ,  NAHAS, Joseph, J.

Inventor： NAHAS, Joseph, J.

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C8/10

Abstract: Each memory cell of an MRAM (800, 1000) that uses toggle writing is written by applying to the memory cell (R 0 ) a first field (t1), then a combination of the first field and the second field (t2), then the second field (t3). The removal of the second field (t4) ultimately completes the writing of the memory cell (R 0 ). The combination of the first field and the second field is known to saturate a portion, the synthetic antiferromagnet (SAF), of the MRAM cell (R 0 ) being written. This can result in not knowing which logic state is ultimately written. This is known to be worsened at higher temperatures (408, 410, 412). To avoid this deleterious saturation, the magnetic field is reduced during the time (t2) when both fields are applied. This is achieved by reducing the current that provides these fields from the current that is applied when only one of the fields is applied.

Abstract translation: 使用切换写入的MRAM（800,1000）的每个存储单元通过将第一场（t1）应用于存储器单元（R SUB> 0）来写入，然后将第一场和 第二场（t2），然后是第二场（t3）。 第二场（t4）的移除最终完成对存储器单元（R 0> 0）的写入。 已知第一场和第二场的组合使正在写入的MRAM单元（R 0> 0）的一部分合成反铁磁体（SAF）饱和。 这可能导致不知道最终写入哪个逻辑状态。 已知在较高温度下恶化（408,410,412）。 为了避免这种有害的饱和，在施加两个场的时间（t2）期间磁场减小。 这是通过减少当仅应用其中一个字段时应用的当前电流来提供这些字段的电流来实现的。

公开(公告)号：WO2007036047B1

公开(公告)日：2007-05-24

申请号：PCT/CA2006001606

申请日：2006-09-29

Applicant: MOSAID TECHNOLOGIES INC ,  KIM JIN-KI ,  PYEON HONG BEOM

Inventor： KIM JIN-KI ,  PYEON HONG BEOM

IPC: G11C11/4193 ,  G11C11/4197 ,  G11C16/06

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

Abstract: An apparatus, system, and method for controlling data transfer between a serial data link interface and memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple serial data links and multiple memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract translation: 公开了一种用于控制半导体存储器中的串行数据链路接口和存储体之间的数据传输的装置，系统和方法。 在一个示例中，公开了具有多个串行数据链路的闪存器件和多个存储器组，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：WO2007053764A2

公开(公告)日：2007-05-10

申请号：PCT/US2006042923

申请日：2006-11-01

Applicant: HEWLETT PACKARD DEVELOPMENT CO ,  WU WEI ,  KUEKES PHILIP J ,  WILLIAMS R STANLEY

Inventor： WU WEI ,  KUEKES PHILIP J ,  WILLIAMS R STANLEY

IPC: G11C8/10

CPC classification number: G11C13/02 ,  B82Y10/00 ,  G11C8/10 ,  G11C11/54 ,  G11C13/0023 ,  G11C2213/77 ,  G11C2213/81 ,  H01L27/10 ,  H01L27/285 ,  Y10S977/762 ,  Y10S977/932

Abstract: Various embodiments of the present invention are directed to crossbar array designs that interfaces wires to address wires, despite misalignments between electrical components and wires. In one embodiment, a nanoscale device may be composed of a first layer of two or more wires (1501-1511) and a second layer of two or more address wires (1512-1523) that overlays the first layer. The nanoscale device may also include an intermediate layer (704-804) positioned between the first layer and the second layer. Two or more redundant electrical component patterns (1400) may be fabricated within the intermediate layer so that one or more of the electrical component patterns is aligned with the first and second layers.

Abstract translation: 尽管电气部件和电线之间未对准，本发明的各种实施例针对交叉开关阵列设计，其将导线连接到地址导线。 在一个实施例中，纳米级器件可以由覆盖第一层的两个或更多个导线（1501-1511）的第一层和两个或更多个地址导线（1512-1523）的第二层组成。 纳米级装置还可以包括位于第一层和第二层之间的中间层（704-804）。 可以在中间层内制造两个或更多冗余电部件图案（1400），使得一个或多个电部件图案与第一和第二层对齐。

公开(公告)号：WO2007018661A2

公开(公告)日：2007-02-15

申请号：PCT/US2006/018760

申请日：2006-05-12

Applicant: LATTICE SEMICONDUCTOR CORPORATION

Inventor： DE LA CRUZ, Louis ,  WHITE, Allen ,  VERNENKER, Hemanshu

IPC: G11C8/00

CPC classification number: G11C8/10

Abstract: Systems and methods are disclosed herein to provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal. The registered address signal provides at least a true and a complement signal, with the true and complement signal set to approximately the same logical value upon assertion of the reset signal. An address pre-decoder, coupled to the address register, at least partially decodes the registered address signal to provide a pre-decoded output signal. A wordline driver, coupled to the address pre-decoder, receives a wordline enable signal and the pre-decoded output signal and provides a wordline signal based on the pre-decoded output signal upon assertion of the wordline enable signal.

Abstract translation: 这里公开的系统和方法为存储器提供了改进的地址解码技术。 例如，根据本发明的实施例，集成电路包括地址寄存器，该地址寄存器接收复位信号，时钟信号和地址信号，并提供寄存的地址信号。 寄存的地址信号提供至少一个真信号和一个补码信号，一旦声明复位信号，真信号和补码信号就被设置为大致相同的逻辑值。 耦合到地址寄存器的地址预解码器至少部分解码寄存的地址信号以提供预解码的输出信号。 耦合到地址预解码器的字线驱动器接收字线使能信号和预解码输出信号，并在断言字线使能信号时基于预解码输出信号提供字线信号。

公开(公告)号：WO2007011037A1

公开(公告)日：2007-01-25

申请号：PCT/JP2006/314522

申请日：2006-07-21

Applicant: 松下電器産業株式会社 ,  川島 敬司

Inventor： 川島 敬司

IPC: G11C16/06 ,  G06F12/06 ,  G09G5/24 ,  G11C11/413 ,  G11C16/02

CPC classification number: G11C16/06 ,  G06T1/60 ,  G09G5/24 ,  G09G5/395 ,  G09G2340/0492 ,  G09G2360/123 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1042 ,  G11C7/1051 ,  G11C8/10

Abstract: 　複数のメモリアドレスに格納されている所定のビットデータを、メモリ装置からのデータ出力として読み出すことでメモリの削減と処理の負担を軽減することができるメモリ装置およびメモリ応用装置を提供することを目的とする。 　本発明のメモリ装置は、バッファ回路（２０ 0 ，・・・，２ｎ－１ n-1 ）が出力するメモリセル（０ 00 ，・・・，ｎ－１ m-1n-1 ）のデータを、各メモリセルアレイ（１ 0 ）ないし（１ n-1 ）から１ビットずつ、または１つのメモリセルアレイからｎビットのいずれかを選択出力できるマルチプレクサ（３０ 1 ，・・・，３ｎ－１ n-2 ）を備える。

Abstract translation: 具有缩小比例的存储器，并通过读取存储在存储器地址中的预定位数据作为从存储器和存储器应用器件输出的数据来实现处理减少。 存储器具有用于选择性地在存储单元中输出数据的多路复用器（30 ... 1，...，3n-1＆lt; n-2＆lt; ，...，n-1，m-1n-1）由缓冲电路输出（20，...，2n-1，n-1， / SUB>）从一个存储单元阵列（1 <0> 1 <1> n-1）1比特或1比特。

公开(公告)号：WO2006115980A1

公开(公告)日：2006-11-02

申请号：PCT/US2006/014888

申请日：2006-04-19

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L. P. ,  KUEKES, Phillip, J. ,  WILLIAMS, Stanley, R.

Inventor： KUEKES, Phillip, J. ,  WILLIAMS, Stanley, R.

IPC: G11C13/02

CPC classification number: G11C8/10 ,  B82Y10/00 ,  G11C13/0023 ,  G11C13/02 ,  G11C2213/77 ,  G11C2213/81 ,  Y10S977/938

Abstract: Various embodiments of the present invention are directed to electronic means for reading the content of a nanowire-crossbar memory. In one embodiment of the present invention, a microscale or sub-microscale signal line (402) is interconnected with one set of parallel nanowires (310-315) emanating from a nanowire-crossbar memory by configurable, nanowire-junction switches (404). The microscale or sub-microscale signal line (402) serves as a single-wire multiplexer, allowing the contents of any particular single-bit atorage element (316) within the nanowire-crossbar memory to be read.

Abstract translation: 本发明的各种实施例涉及用于读取纳米线交叉存储器的内容的电子装置。 在本发明的一个实施例中，微米级或亚微米级信号线（402）与通过可配置的纳米线结开关（404）从纳米线交叉存储器发出的一组平行纳米线（310-315）互连。 微尺度或亚微米信号线（402）用作单线多路复用器，允许读取纳米线交叉存储器内的任何特定单位位元件（316）的内容。