公开(公告)号：WO2018236369A1

公开(公告)日：2018-12-27

申请号：PCT/US2017/038507

申请日：2017-06-21

申请人： INTEL CORPORATION ,  CHAWLA, Jasmeet S. ,  MANIPATRUNI, Sasikanth ,  LIN, Chia-Ching ,  NIKONOV, Dmitri E. ,  YOUNG, Ian A.

发明人： CHAWLA, Jasmeet S. ,  MANIPATRUNI, Sasikanth ,  LIN, Chia-Ching ,  NIKONOV, Dmitri E. ,  YOUNG, Ian A.

IPC分类号： H01L43/02 ,  H01L43/08 ,  H01L43/10

CPC分类号： H01L43/10 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

摘要： Embodiments are generally directed to enhanced materials processing for magneto-electric spin orbit (MESO) devices. An embodiment of an apparatus includes a first transistor and a second transistor, each transistor including a gate electrode, a first junction region, and a second junction region; a set of lines including alternating ferromagnetic material lines and non-magnetic metal interconnect lines fabricated in a wafer, the plurality of lines including metal interconnect lines to provide connections for the junction regions of the first and second transistors, including connections to provide power and control; and a MESO device including a first magnet and a second magnet, the set of lines including ferromagnetic material lines for fabrication of the MESO device magnets.

公开(公告)号：WO2018125248A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069638

申请日：2016-12-31

申请人： INTEL CORPORATION ,  MANIPATRUNI, Sasikanth ,  CHAWLA, Jasmeet S. ,  WIEGAND, Christopher J. ,  NIKONOV, Dmitri E. ,  GOLONZKA, Oleg ,  YOUNG, Ian A.

发明人： MANIPATRUNI, Sasikanth ,  CHAWLA, Jasmeet S. ,  WIEGAND, Christopher J. ,  NIKONOV, Dmitri E. ,  GOLONZKA, Oleg ,  YOUNG, Ian A.

IPC分类号： H01L43/10 ,  H01L43/02 ,  H01L43/08

CPC分类号： H01L43/08 ,  G11C11/161 ,  H01F10/1936 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/222 ,  H01L43/10

摘要： Embodiments are generally directed to Heusler alloy based magnetic tunnel junctions and refractory interconnects. An embodiment of an apparatus includes a magnetic tunnel junction (MTJ) stack of an MRAM (Magnetoresistive Random Access Memory), the MTJ stack including a free magnetic layer and a fixed magnetic later, wherein the magnetic tunnel junction stack including one or more Heusler alloys; and metal interconnects for the MRAM, wherein the metal interconnects include one or more refractory metals, Silicides or Germinides of Nickel or Cobalt, refractory Heusler alloy, or Silicides of Heusler alloy.

公开(公告)号：WO2018118091A1

公开(公告)日：2018-06-28

申请号：PCT/US2016/068584

申请日：2016-12-23

申请人： INTEL CORPORATION ,  CHAWLA, Jasmeet S. ,  MANIPATRUNI, Sasikanth ,  BRISTOL, Robert L. ,  LIN, Chia-Ching ,  NIKONOV, Dmitri E. ,  YOUNG, Ian A.

发明人： CHAWLA, Jasmeet S. ,  MANIPATRUNI, Sasikanth ,  BRISTOL, Robert L. ,  LIN, Chia-Ching ,  NIKONOV, Dmitri E. ,  YOUNG, Ian A.

IPC分类号： H01L43/02 ,  H01L43/10 ,  H01L43/12

摘要： Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

公开(公告)号：WO2016175782A1

公开(公告)日：2016-11-03

申请号：PCT/US2015/028209

申请日：2015-04-29

申请人： INTEL CORPORATION ,  CHAWLA, Jasmeet S. ,  HOURANI, Rami ,  KOBRINSKY, Mauro J. ,  GSTREIN, Florian ,  CLENDENNING, Scott B. ,  ROBERTS, Jeanette M.

发明人： CHAWLA, Jasmeet S. ,  HOURANI, Rami ,  KOBRINSKY, Mauro J. ,  GSTREIN, Florian ,  CLENDENNING, Scott B. ,  ROBERTS, Jeanette M.

IPC分类号： H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2221/1063

摘要： A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.

摘要翻译： 可以形成包括导电迹线和导电通孔的导电路径结构，其中导电通孔直接接触导电迹线。 在一个实施例中，可以通过在导电迹线上形成介电材料层来形成导电路径结构。 可以通过介电材料层形成通孔开口以暴露导电迹线的一部分，并且阻挡层可以仅来自导电迹线的暴露部分。 可以在通孔开口的侧壁上形成阻挡线，然后可以去除阻挡层。 然后可以在通孔开口内形成导电通孔，其中导电通孔直接接触导电迹线。