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    IN SITU SURFACE CONTAMINANT REMOVAL FOR ION IMPLANTING
    1.
    发明申请
    IN SITU SURFACE CONTAMINANT REMOVAL FOR ION IMPLANTING 审中-公开
    用于离子植入的现场表面污染物去除

    公开(公告)号：WO2006023637A2

    公开(公告)日：2006-03-02

    申请号：PCT/US2005029387

    申请日：2005-08-18

    Applicant: VARIAN SEMICONDUCTOR EQUIPEMEN ,  WALTHER STEVE ,  MEHTA SANDEEP ,  VARIAM NAUSHAD ,  JEONG UKYO

    Inventor： WALTHER STEVE ,  MEHTA SANDEEP ,  VARIAM NAUSHAD ,  JEONG UKYO

    IPC: H01L21/302 ,  C03C25/68 ,  C23F1/00

    CPC classification number: C03C23/0055 ,  B08B7/0057 ,  B08B7/0071 ,  C03C15/00 ,  C03C23/002 ,  H01J37/321 ,  H01J37/32412 ,  H01J2237/335 ,  H01L21/02046 ,  H01L21/26513

    Abstract: Methods and apparatus that introduce, within the ion implant chamber or an isolated chamber in communication therewith, the capability to remove contaminants and oxide surface layers on a wafer surface prior to ion implantation, are disclosed. The mechanisms for removal of contaminants include conducting: a low energy plasma etch, heating the wafer and application of ultraviolet illumination, either in combination or individually. As a result, implantation can occur immediately after the cleaning/preparation process without the contamination potential of exposure of the wafer to an external environment. The preparation allows for the removal of surface contaminants, such as water vapor, organic materials and surface oxides.

    Abstract translation: 公开了在离子注入室或与之连通的隔离室内引入在离子注入之前去除晶片表面上的污染物和氧化物表面层的能力的方法和装置。 去除污染物的机理包括：组合或单独地进行低能量等离子体蚀刻，加热晶片和施加紫外线照明。 结果，可以在清洁/制备过程之后立即进行植入，而没有将晶片暴露于外部环境的污染潜力。 该制剂允许去除表面污染物，例如水蒸汽，有机材料和表面氧化物。

    REDUCTION OF SOURCE AND DRAIN PARASITIC CAPACITANCE IN CMOS DEVICES
    2.
    发明申请
    REDUCTION OF SOURCE AND DRAIN PARASITIC CAPACITANCE IN CMOS DEVICES 审中-公开
    降低CMOS器件中的源极和漏极寄生电容

    公开(公告)号：WO2006026180A3

    公开(公告)日：2006-08-03

    申请号：PCT/US2005029454

    申请日：2005-08-18

    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ,  EROKHIN YURI ,  JEONG UKYO ,  SCHEUER JAY T ,  WALTHER STEVEN R

    Inventor： EROKHIN YURI ,  JEONG UKYO ,  SCHEUER JAY T ,  WALTHER STEVEN R

    IPC: H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78

    CPC classification number: H01L21/2236 ,  H01L29/66575

    Abstract: A method for fabricating a semiconductor-based device includes providing a doped semiconductor substrate, introducing a second dopant into the substrate to define a pn junction, and introducing a neutralizing species into the substrate in the neighborhood of the pn junction to reduce a capacitance associated with the pn junction. A semiconductor-based device includes a semiconductor substrate having first and second dopants, and a neutralizing species. The first and second dopants define a pn junction, and the neutralizing species neutralizes a portion of the first dopant in the neighborhood of the pn junction to decrease a capacitance associated with the pn junction.

    Abstract translation: 一种用于制造基于半导体的器件的方法包括提供掺杂的半导体衬底，将第二掺杂剂引入到衬底中以限定pn结，并将中和物质引入到pn结附近的衬底中，以减少与 pn结。 基于半导体的器件包括具有第一和第二掺杂剂的半导体衬底和中和物质。 第一和第二掺杂剂限定pn结，并且中和物质中和pn结附近的第一掺杂剂的一部分以减少与pn结相关联的电容。

    REDUCTION OF SOURCE AND DRAIN PARASITIC CAPACITANCE IN CMOS DEVICES
    5.
    发明申请
    REDUCTION OF SOURCE AND DRAIN PARASITIC CAPACITANCE IN CMOS DEVICES 审中-公开
    CMOS器件中源极和漏极寄生电容的降低

    公开(公告)号：WO2006026180A2

    公开(公告)日：2006-03-09

    申请号：PCT/US2005/029454

    申请日：2005-08-18

    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. ,  EROKHIN, Yuri ,  JEONG, Ukyo ,  SCHEUER, Jay, T. ,  WALTHER, Steven, R.

    Inventor： EROKHIN, Yuri ,  JEONG, Ukyo ,  SCHEUER, Jay, T. ,  WALTHER, Steven, R.

    IPC: H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78

    CPC classification number: H01L21/2236 ,  H01L29/66575

    Abstract: A method for fabricating a semiconductor-based device includes providing a doped semiconductor substrate, introducing a second dopant into the substrate to define a pn junction, and introducing a neutralizing species into the substrate in the neighborhood of the pn junction to reduce a capacitance associated with the pn junction. A semiconductor-based device includes a semiconductor substrate having first and second dopants, and a neutralizing species. The first and second dopants define a pn junction, and the neutralizing species neutralizes a portion of the first dopant in the neighborhood of the pn junction to decrease a capacitance associated with the pn junction.

    Abstract translation: 用于制造基于半导体的器件的方法包括提供掺杂的半导体衬底，将第二掺杂剂引入到衬底中以限定pn结，并且将中和物质引入衬底中的邻近衬底 pn结以减小与pn结相关联的电容。 基于半导体的器件包括具有第一和第二掺杂剂以及中和物质的半导体衬底。 第一和第二掺杂剂限定pn结，并且中和物质中和pn结附近的第一掺杂剂的一部分，以减小与pn结相关的电容。

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