公开(公告)号：WO2015147784A1

公开(公告)日：2015-10-01

申请号：PCT/US2014/031603

申请日：2014-03-24

Applicant: INTEL CORPORATION ,  GLASS, Glenn, A. ,  MURTHY, Anand, S. ,  AUBERTINE, Daniel, B. ,  JOSHI, Subhash, M.

Inventor： GLASS, Glenn, A. ,  MURTHY, Anand, S. ,  AUBERTINE, Daniel, B. ,  JOSHI, Subhash, M.

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for transistor channel applications). The sculpting and cladding can be performed when the channel region of the fins are re-exposed after the dummy gate used in the replacement gate process is removed. The sculpting includes performing a trim etch on the re-exposed channel region of the fins to narrow a width of the fins (e.g., by 2-6 nm). A cladding layer, which may include germanium (Ge) or silicon germanium (SiGe), can then be deposited on the trimmed fins, leaving the source/drain regions of the fins unaffected. The sculpting and cladding may be performed in-situ or without air break to increase the quality of the trimmed fins (e.g., as compared to an ex-situ process).

Abstract translation: 公开了在替换栅极处理（例如，用于晶体管通道应用）期间在半导体衬底上雕刻和包覆鳍片的沟道区域的技术。 在更换闸门处理中使用的虚拟门被去除后，当鳍片的通道区域再曝光时，可以进行雕刻和包层。 雕刻包括在鳍片的再曝光的通道区域上进行修整蚀刻，以使翅片的宽度变窄（例如，2-6nm）。 然后可以将包括锗（Ge）或硅锗（SiGe）的包覆层沉积在修整的翅片上，留下散热片的源极/漏极区域不受影响。 雕刻和包层可以在原位或无空气破裂的情况下进行，以提高修剪的翅片的质量（例如，与非原位工艺相比）。

公开(公告)号：WO2015099680A1

公开(公告)日：2015-07-02

申请号：PCT/US2013/077593

申请日：2013-12-23

Applicant: INTEL CORPORATION ,  GLASS, Glenn A. ,  MURTHY, Anand S. ,  AUBERTINE, Daniel B. ,  JOSHI, Subhash M.

Inventor： GLASS, Glenn A. ,  MURTHY, Anand S. ,  AUBERTINE, Daniel B. ,  JOSHI, Subhash M.

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/304 ,  H01L21/30604 ,  H01L27/0886 ,  H01L27/105 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7849

Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.

Abstract translation: 可以通过用于尺寸雕刻的射频（RF）等离子体和/或热处理来修改晶体管鳍元件（例如，鳍或三栅极）。 蚀刻的，变薄的翅片可以通过首先形成较宽的单晶翅片形成，并且在较宽翅片之间沉积沟槽氧化物材料之后，使用第二蚀刻蚀刻较宽的翅片以形成具有未损坏的顶部和侧壁的较窄的单晶翅片，用于外延生长活性 通道材料。 第二蚀刻可以去除顶表面和较宽翅片的侧壁之间的1nm和15nm之间的厚度。 它可以使用（1）使用低离子能量等离子体处理的氯或氟基化学物质来除去厚度，或者（2）低温热处理，其不会通过能量离子轰击，氧化或留下蚀刻残留物而损坏翅片，这可能会破坏 外延生长质量的第二种材料。

公开(公告)号：WO2013048513A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054459

申请日：2011-09-30

Applicant: INTEL CORPORATION ,  JOSHI, Subhash M. ,  HATTENDORF, Michael

Inventor： JOSHI, Subhash M. ,  HATTENDORF, Michael

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66803

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the doping of fins within non-planar transistors, wherein a conformal blocking material layer, such as a dielectric material, may be used to achieve a substantially uniform doping throughout the non-planar transistor fins.

Abstract translation: 本说明书涉及制造具有非平面晶体管的微电子器件的领域。 本说明书的实施例涉及在非平面晶体管内掺杂鳍片，其中可以使用诸如电介质材料的共形阻挡材料层来实现整个非平面晶体管鳍片的基本上均匀的掺杂。

公开(公告)号：WO2007133440A3

公开(公告)日：2007-11-22

申请号：PCT/US2007/010482

申请日：2007-05-01

Applicant: INTEL CORPORATION ,  RACHMADY, Willy ,  MCINTYRE, Brian ,  HARPER, Michael, K. ,  JOSHI, Subhash, M.

Inventor： RACHMADY, Willy ,  MCINTYRE, Brian ,  HARPER, Michael, K. ,  JOSHI, Subhash, M.

IPC: H01L21/28 ,  H01L21/205 ,  H01L21/203

Abstract: A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high- k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high- k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high- k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high- k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.

公开(公告)号：WO2013048455A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054329

申请日：2011-09-30

Applicant: INTEL CORPORATION ,  JOSHI, Subhash M. ,  HATTENDORF, Michael

Inventor： JOSHI, Subhash M. ,  HATTENDORF, Michael

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.

Abstract translation: 本发明涉及非平面晶体管内的形成源极/漏极结构，其中从非平面晶体管去除翅片间隔物，以便从非平面晶体管鳍片形成源/漏结构， 具有适当材料的平面晶体管鳍片以形成源极/漏极结构。

公开(公告)号：WO2007133440A2

公开(公告)日：2007-11-22

申请号：PCT/US2007010482

申请日：2007-05-01

Applicant: INTEL CORP ,  RACHMADY WILLY ,  MCINTYRE BRIAN ,  HARPER MICHAEL K ,  JOSHI SUBHASH M

Inventor： RACHMADY WILLY ,  MCINTYRE BRIAN ,  HARPER MICHAEL K ,  JOSHI SUBHASH M

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66553

Abstract: A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.

Abstract translation: 晶体管栅极包括具有设置在表面上的一对间隔物的衬底，在隔离体之间保形地沉积在衬底上的高k电介质，共形沉积在高k电介质上并沿着间隔壁侧壁的一部分的凹陷功函数金属 保形地沉积在凹陷功函数金属上的第二功函件金属和沉积在第二功函数金属上的电极金属。 晶体管栅极可以通过将高k电介质保形地沉积到衬底上的间隔物之间​​的沟槽中而形成，从而在高k电介质顶部上共形沉积功函数金属，在功函数金属顶部沉积牺牲掩模，蚀刻部分 牺牲掩模以暴露所述功函数金属的一部分，以及蚀刻所述功函数金属的暴露部分以形成所述凹陷功函数金属。 第二功函数金属和电极金属可以沉积在凹陷功函数金属顶上。