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    TIMING CALIBRATION FOR MULTIMODE I/O SYSTEMS
    1.
    发明申请
    TIMING CALIBRATION FOR MULTIMODE I/O SYSTEMS 审中-公开
    多模I / O系统的时序校准

    公开(公告)号：WO2012118714A2

    公开(公告)日：2012-09-07

    申请号：PCT/US2012026583

    申请日：2012-02-24

    Applicant: RAMBUS INC ,  OH KYUNG SUK ,  BANSAL AKASH

    Inventor： OH KYUNG SUK ,  BANSAL AKASH

    CPC classification number: G06F1/08 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    Abstract: Integrated circuit devices that operate in different modes. In a low data rate mode, data is transferred between the integrated circuit devices at a low data rate, or no data is transferred at all. In a high data rate mode, data is transferred between integrated circuit devices at a high data rate. A transition mode facilitates the transition from the low data rate mode to the high data rate mode. During the transition mode data is transferred between the integrated circuit devices at an intermediate data rate greater than the low data rate but lower than the high data rate. Also during the transition mode, parameters affecting the transmission of data between the integrated circuit devices are calibrated at the high data rate.

    Abstract translation: 在不同模式下工作的集成电路器件。 在低数据速率模式下，以低数据速率在集成电路设备之间传输数据，或完全没有数据传输。 在高数据速率模式下，以高数据速率在集成电路器件之间传输数据。 转换模式有助于从低数据速率模式转换到高数据速率模式。 在转换模式期间，以大于低数据速率但低于高数据速率的中间数据速率在集成电路器件之间传送数据。 而且在转换模式期间，在高数据速率下校准影响集成电路器件之间的数据传输的参数。

    FREQUENCY RESPONSIVE BUS CODING
    3.
    发明申请
    FREQUENCY RESPONSIVE BUS CODING 审中-公开
    频率响应总线编码

    公开(公告)号：WO2010147608A1

    公开(公告)日：2010-12-23

    申请号：PCT/US2009/066253

    申请日：2009-12-01

    Applicant: RAMBUS, INC. ,  OH, Kyung, Suk ,  WILSON, John ,  KIM, Joong-Ho ,  REN, Jihong

    Inventor： OH, Kyung, Suk ,  WILSON, John ,  KIM, Joong-Ho ,  REN, Jihong

    IPC: G06F13/38 ,  G06F13/40 ,  G06F9/00

    CPC classification number: H04L25/49 ,  H04L25/4915

    Abstract: A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels ("DBI_DC") and a measure of a number of logic level transitions relative to a prior signal ("DBI_AC") provides a measure of control that may be used to compensate for both main and predriver switching noise.

    Abstract translation: 数据系统允许基于总线的频率和总线上的切换频率的总线编码，以避免不期望的频率条件，例如谐振条件或与其他电气设备的干扰。 监视一个或多个总线的传输频率并用于控制编码过程，例如，基于数据总线反转（DBI）的编码处理。 使用绝对数量逻辑电平（“DBI_DC”）的度量和相对于先前信号（“DBI_AC”）的逻辑电平转换的数量的度量提供了可用于补偿 主要和预先切换的开关噪声。

    ASYMMETRIC COMMUNICATION ON SHARED LINKS
    4.
    发明申请
    ASYMMETRIC COMMUNICATION ON SHARED LINKS 审中-公开
    共享链接上的不对称通信

    公开(公告)号：WO2009086142A1

    公开(公告)日：2009-07-09

    申请号：PCT/US2008/087743

    申请日：2008-12-19

    Applicant: RAMBUS INC. ,  OH, Kyung Suk ,  WILSON, John ,  WARE, Frederick ,  KIM, WooPoung ,  KIZER, Jade M. ,  LEIBOWITZ, Brian S. ,  LUO, Lei ,  EBLE, John Cronan

    Inventor： OH, Kyung Suk ,  WILSON, John ,  WARE, Frederick ,  KIM, WooPoung ,  KIZER, Jade M. ,  LEIBOWITZ, Brian S. ,  LUO, Lei ,  EBLE, John Cronan

    IPC: G06F13/42 ,  H04L25/49

    CPC classification number: G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

    Abstract translation: 描述了经由共享链路在两个设备之间传递双向数据的系统的实施例。 在这个系统中，数据通过使用单端驱动器的设备之一在共享链路上传输，并且相应的符号由另一个设备使用差分比较电路在共享链路上接收。 数据可以在传输之前被编码为一系列并行码字。 每个共享链路可以传送每个码字中的相应符号，其可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）。 由另一个设备接收到的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。 另一个设备中的解码器可以从差分比较电路的输出中解码相应的并行符号集合以恢复编码的数据。

    STRUCTURE FOR DELIVERING POWER
    7.
    发明申请
    STRUCTURE FOR DELIVERING POWER 审中-公开
    传递力的结构

    公开(公告)号：WO2013048628A1

    公开(公告)日：2013-04-04

    申请号：PCT/US2012/050730

    申请日：2012-08-14

    Applicant: RAMBUS INC. ,  OH, Kyung Suk ,  SCHMITT, Ralf M. ,  FENG, Yijiong

    Inventor： OH, Kyung Suk ,  SCHMITT, Ralf M. ,  FENG, Yijiong

    IPC: G06F1/18 ,  G06F1/26

    CPC classification number: H05K1/0216 ,  H01B5/02 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

    Abstract translation: 描述用于传送电力的结构。 在一些实施例中，该结构可以包括设置在两层或更多层上的导体。 具体地，该结构可以包括设置在第一层上并基本上沿着电流的预期方向取向的第一组交叉导体。 第一组交叉导体中的至少一个导体可以保持在第一电压，并且第一组交叉导体中的至少一个导体可以保持在第二电压，其中第二电压不同于第一电压。 该结构还可以包括设置在第二层上的导电结构，其中第二层不同于第一层，并且其中导电结构中的至少一个导体保持在第一电压。

    METHODS AND SYSTEMS FOR REDUCING SUPPLY AND TERMINATION NOISE
    8.
    发明申请
    METHODS AND SYSTEMS FOR REDUCING SUPPLY AND TERMINATION NOISE 审中-公开
    减少供应和终止噪声的方法和系统

    公开(公告)号：WO2011041064A2

    公开(公告)日：2011-04-07

    申请号：PCT/US2010/047466

    申请日：2010-09-01

    Applicant: RAMBUS INC. ,  OH, Kyung, Suk

    Inventor： OH, Kyung, Suk

    IPC: G11C7/10

    CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254

    Abstract: Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.

    Abstract translation: 描述的是第一集成电路（IC）中的通信系统通过单端通信信道与第二IC进行通信。 双向参考通道在第一和第二IC之间延伸并在两端终止。 参考通道每端的终端阻抗支持用于在不同方向上传送信号的不同模式。 可以针对每个信令方向优化参考信道的终止阻抗。

    ASYMMETRIC COMMUNICATION ON SHARED LINKS
    9.
    发明申请
    ASYMMETRIC COMMUNICATION ON SHARED LINKS 审中-公开
    共享链路上的不对称通信

    公开(公告)号：WO2009086142A4

    公开(公告)日：2009-10-15

    申请号：PCT/US2008087743

    申请日：2008-12-19

    Applicant: RAMBUS INC ,  OH KYUNG SUK ,  WILSON JOHN ,  WARE FREDERICK ,  KIM WOOPOUNG ,  KIZER JADE M ,  LEIBOWITZ BRIAN S ,  LUO LEI ,  EBLE JOHN CRONAN

    Inventor： OH KYUNG SUK ,  WILSON JOHN ,  WARE FREDERICK ,  KIM WOOPOUNG ,  KIZER JADE M ,  LEIBOWITZ BRIAN S ,  LUO LEI ,  EBLE JOHN CRONAN

    IPC: G06F13/42 ,  H04L25/49

    CPC classification number: G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

    Abstract translation: 描述了经由共享链路在两个设备之间传送双向数据的系统的实施例。 在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。 数据可以在传输之前被编码为一系列并行码字。 每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。 由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。 另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

    RECEIVER FOR MULTI-WIRE COMMUNICATION WITH REDUCED INPUT CAPACITANCE
    10.
    发明申请
    RECEIVER FOR MULTI-WIRE COMMUNICATION WITH REDUCED INPUT CAPACITANCE 审中-公开
    接收器用于具有降低输入电容的多线通信

    公开(公告)号：WO2009086078A1

    公开(公告)日：2009-07-09

    申请号：PCT/US2008/087639

    申请日：2008-12-19

    Applicant: RAMBUS INC. ,  WARE, Frederick ,  WILSON, John ,  OH, Kyung Suk ,  LEIBOWITZ, Brian S. ,  KIZER, Jade M. ,  LUO, Lei

    Inventor： WARE, Frederick ,  WILSON, John ,  OH, Kyung Suk ,  LEIBOWITZ, Brian S. ,  KIZER, Jade M. ,  LUO, Lei

    IPC: G06F13/42 ,  H04L25/49

    CPC classification number: G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Embodiments of a device that receives and decodes a series of parallel symbol sets over a series of time intervals is described. In this device, symbols in a respective parallel symbol set are received on nodes. Each node receives a respective symbol, which can have one of two possible logical values ( e.g ., a logic 0 or a logic 1). Differential amplifiers in the device provide primary comparison results, each of which compares symbols received on pairs of the links, and generation circuits in the device provide secondary comparison results from the primary comparison results. A decoder in the device decodes a respective parallel symbol set from the primary and secondary comparison results to recover encoded data.

    Abstract translation: 描述了在一系列时间间隔内接收并解码一系列并行符号集的设备的实施例。 在这个装置中，各个并行符号集中的符号在节点上被接收。 每个节点接收相应的符号，该符号可以具有两个可能的逻辑值之一（例如，逻辑0或逻辑1）。 设备中的差分放大器提供主要比较结果，每个比较结果比较在链路对上接收的符号，并且设备中的发生电路提供来自主要比较结果的次级比较结果。 设备中的解码器从主要和次要比较结果解码相应的并行符号集以恢复编码数据。

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