公开(公告)号：WO2013131821A1

公开(公告)日：2013-09-12

申请号：PCT/EP2013/054169

申请日：2013-03-01

Applicant: ABB TECHNOLOGY AG

Inventor： RAHIMO, Munaf ,  CORVASCE, Chiara ,  VOBECKY, Jan ,  OTANI, Yoichi

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/739 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L29/66325 ,  H01L21/2251 ,  H01L21/283 ,  H01L21/324 ,  H01L29/0834 ,  H01L29/45 ,  H01L29/456 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/8613

Abstract: • - providing a wafer (1) of a first conductivity type, which wafer has a first main side (11) and a second main side (15) opposite to the first main side (11 ), • - applying on the second main side (15) at least one of a dopant of the first conductivity type for forming a layer (2) of the first conductivity type and a dopant of a second conductivity type for forming a layer (2) of the second conductivity type, • - afterwards depositing a Titanium layer (3) on the second main side (15), • - laser annealing the Titanium deposition layer (3) so that simultaneously an intermetal compound layer (35) is formed at the interface between the Titanium deposition layer (3) and the wafer (1) and the dopant is diffused into the wafer (1), • - creating a first metal electrode layer (4) on the second side (15).

Abstract translation: 。 - 提供第一导电类型的晶片（1），该晶片具有与第一主侧（11）相对的第一主侧（11）和第二主侧（15）。 - 在第二主侧（15）上施加第一导电类型的掺杂剂中的至少一种，用于形成第一导电类型的层（2）和用于形成第二导电类型的层（2）的第二导电类型的掺杂剂 第二导电类型。 - 之后在第二主侧（15）上沉积钛层（3）。 - 钛化沉积层（3）的激光退火，使得在钛沉积层（3）和晶片（1）之间的界面处同时形成金属间化合物层（35），掺杂剂扩散到晶片（1）中， ，。 - 在第二侧（15）上形成第一金属电极层（4）。

公开(公告)号：WO2011058035A2

公开(公告)日：2011-05-19

申请号：PCT/EP2010/067175

申请日：2010-11-10

Applicant: ABB TECHNOLOGY AG ,  RAHIMO, Munaf ,  KOPTA, Arnost ,  VOBECKY, Jan ,  JANISCH, Wolfgang

Inventor： RAHIMO, Munaf ,  KOPTA, Arnost ,  VOBECKY, Jan ,  JANISCH, Wolfgang

IPC: H01L29/739 ,  H01L21/331 ,  H01L29/06

CPC classification number: H01L29/7395 ,  H01L29/0611 ,  H01L29/66333

Abstract: A maximum-punch-through semiconductor device (1) such as an insulated gate bipolar transistor (IGBT) or a diode and a method for producing same are proposed. The MPT semiconductor device (1) comprises at least a two-layer structure having layers in the following order: an emitter metallization (3), a channel region (10), a base layer (4) with a predetermined doping concentration ND, a buffer layer (5) and a collector metallization (7). A thickness W of the base layer is determined by Formula (I), wherein a punch-through voltage V pt of the semiconductor device is between 70 % and 99 % of a break down voltage V bd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer (4) between the junction to the channel region (10) and the buffer layer (5). With the design rule provided, an IGBT or diode having low electrical losses and soft turn-off characteristics may be provided. A shallow buffer layer (5) having a thickness of less than 10 μm may be used. Such thin buffer layer may be easily produced using for example ion implantation techniques.

Abstract translation: 提出了诸如绝缘栅双极型晶体管（IGBT）或二极管的最大穿通型半导体器件（1）及其制造方法。 MPT半导体器件（1）包括至少两层结构，其具有以下顺序的层：发射极金属化部（3），沟道区（10），具有预定掺杂浓度ND的基极层（4）， 缓冲层（5）和集电极金属化层（7）。 基层的厚度W由公式（I）确定，其中半导体器件的穿通电压V pt是断开电压V in的70％和99％之间， 并且其中厚度W是在到沟道区（10）的结与缓冲层（5）之间的基极层（4）的最小厚度。 利用提供的设计规则，可以提供具有低电损耗和软关断特性的IGBT或二极管。 可以使用厚度小于10μm的浅缓冲层（5）。 这种薄缓冲层可以使用例如离子注入技术容易地制造。

公开(公告)号：WO2016016427A1

公开(公告)日：2016-02-04

申请号：PCT/EP2015/067653

申请日：2015-07-31

Applicant: ABB TECHNOLOGY AG

Inventor： BELLINI, Marco ,  VOBECKY, Jan

IPC: H01L29/74 ,  H01L29/08

CPC classification number: H01L29/7428 ,  H01L29/0839 ,  H01L29/66363 ,  H01L29/74

Abstract: A thyristor, in particular a phase control thyristor, is disclosed which comprises: a) a semiconductor slab, in particular a semiconductor waver or die, in which a thyristor structure is formed, b) a cathode metallization formed on a cathode region on a cathode side surface of the semiconductor slab, c) a gate metallization formed on a gate region on the cathode side surface of the semiconductor slab, d) a plurality of N discrete emitter shorts, arranged at points P, in the cathode re¬ gion, said points having point locations x,, with i e {1;...; Λ/}, e) the points P, defining a Delaunay triangulation comprising a plurality of trian¬ gles Ty with ye {1;...; M), wherein f ) for a first subset of triangles T/ with / e Si _≡ {1;...; M), g) with each triangle T/ being characterized by a geometric quantity having values qjj with / e Si _≡ {1;...; M), said geometric quantity having a mean value μ, and i) a coefficient of variation of the values qjj with / e Si is smaller than 0.1, preferably smaller than 0.05, and/or ii) an absolute value of a skewedness of the geometric quantities qT,/with / e Si is smaller than 5, preferably smaller than 1, and/or iii) a Kurtosis of the geometric quantities q-r,/ with / e Si is smaller than 20, preferably smaller than 10, and/or iv) for a second subset of triangles Tm with m e S2

Abstract translation: 公开了一种晶闸管，特别是相位控制晶闸管，其包括：a）形成有晶闸管结构的半导体板，特别是半导体流体或管芯，b）形成在阴极上的阴极区上的阴极金属化 半导体板的侧表面，c）形成在半导体板的阴极侧表面上的栅极区上的栅极金属化，d）布置在阴极区中的点P处的多个N个离散发射极短路，所述 点具有点位置x ,,即{1; ...; Λ/}，e）点P，定义一个Delaunay三角剖分，包括多个三角形Ty，你们{1; ...; M），其中f）对于第一子集的三角形T /与/ e Si_≡{1; ...; M），g），其中每个三角形T /的特征在于具有值为qjj的几何量，其中/ e Si_≡{1; ...; M），所述几何量具有平均值μ，i）与/ e Si的值qjj的变化系数小于0.1，优选小于0.05，和/或ii）所述几何量的偏差的绝对值 几何量qT，/ / e Si小于5，优选小于1，和/或iii）几何量qr，/ / / Si的峰值小于20，优选小于10，和/或 iv）对于第二子集的三角形Tm，其中，与S2相对应的几何量qr，m与其平均值偏离大于预定量，特别是大于30％，其中， （1）数量qj，m的标准偏差与me S2的乘数和几何量qi的平均值，/ / e Si小于1，优选小于0.1，和/或（2） 在第二子集中的多个三角形的商和第一子集中的多个三角形的商小于1.0×10 -2，优选小于0.5× 10" 3。 还公开了制造这种晶闸管的方法。

公开(公告)号：WO2012041836A1

公开(公告)日：2012-04-05

申请号：PCT/EP2011/066740

申请日：2011-09-27

Applicant: ABB TECHNOLOGY AG ,  VOBECKY, Jan ,  RAHIMO, Munaf

Inventor： VOBECKY, Jan ,  RAHIMO, Munaf

IPC: H01L29/06 ,  H01L29/747 ,  H01L29/87 ,  H01L29/861 ,  H01L21/329

CPC classification number: H01L29/74 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/102 ,  H01L29/66136 ,  H01L29/66363 ,  H01L29/8613

Abstract: A bipolar non-punch-through power semiconductor device is provided. It comprises a semiconductor wafer (2) and a first electrical contact on a first main side and a second electrical contact on a second main side. The wafer (2) comprises an inner region (22) with a wafer thickness (23) and a termination region (24), which surrounds the inner region (22) and in which the wafer thickness (23) is reduced at least on the first main side with a negative bevel. The semiconductor wafer (2) comprises at least a two-layer structure with layers of different conductivity types: - a drift layer (26) of a first conductivity type, a first layer of a second conductivity type directly connected to the drift layer (26) on the first main side and contacting the first electrical contact, which first layer extends to a first layer depth, and - a second layer of the second conductivity type, which is arranged in the termination region (24) on the first main side up to a second layer depth. The second layer depth is larger than the first layer depth, which first layer depth is at most 45 μm. The doping concentration of the second layer is lower than the doping concentration of the first layer.

Abstract translation: 提供了一种双极非穿通功率半导体器件。 它包括半导体晶片（2）和第一主侧上的第一电触点和第二主侧上的第二电触点。 晶片（2）包括具有晶片厚度（23）的内部区域（22）和围绕内部区域（22）的端接区域（24），并且晶片厚度（23）至少在 第一主面有负斜面。 半导体晶片（2）至少包括具有不同导电类型的层的至少两层结构： - 第一导电类型的漂移层（26），直接连接到漂移层（26）的第二导电类型的第一层 ）并且与第一电极接触（第一层延伸到第一层深度）接触，并且第二导电类型的第二层布置在第一主侧上的端接区域（24）中 到第二层深度。 第二层深度大于第一层深度，第一层深度最大为45μm。 第二层的掺杂浓度低于第一层的掺杂浓度。

公开(公告)号：WO2009062876A1

公开(公告)日：2009-05-22

申请号：PCT/EP2008/065030

申请日：2008-11-06

Applicant: ABB TECHNOLOGY AG ,  RAHIMO, Munaf ,  VOBECKY, Jan ,  KOPTA, Arnost

Inventor： RAHIMO, Munaf ,  VOBECKY, Jan ,  KOPTA, Arnost

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/32 ,  H01L21/331 ,  H01L21/263

CPC classification number: H01L29/7395 ,  H01L21/266 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66333

Abstract: A method for manufacturing a reverse-conducting insulated gate bipolar transistor comprises the following steps: - On a wafer of first conductivity type with a first side and a second side opposite the first side, a second layer of a second conductivity type and at least one third layer of the first conductivity type, which is surrounded by the second layer, are created on the first side. The part of the wafer, which has an unamended doping in the finalized RC-IGBT, forms a first layer. - Afterwards a fifth electrically insulating layer is created on the first side, which partially covers the at least one third layer, the second layer and the first layer. - An electrically conductive fourth layer is created on the first side, which is electrically insulated from the wafer by the fifth layer. The at least one third layer, the fourth layer and the fifth layer are created in such a way that they form a first opening above the second layer. - A first electrical contact is created on the first side, which is in direct electrical contact to the second layer and the third layer. - At least one sixth layer of the second conductivity type and at least one seventh layer of the first conductivity type are created on the second side. The at least one sixth and seventh layers are arranged alternately in a plane. - A second electrical contact is created on the second side, which is in direct electrical contact to the at least one sixth and seventh layer. - After the creation of the fourth and fifth layers a ninth layer, formed as a defect layer, is created by implantation of ions on the first side through the first opening using at least the fourth and fifth layer as a first mask.

Abstract translation: 一种用于制造反向导通绝缘栅双极晶体管的方法包括以下步骤： - 在第一导电类型的晶片上具有第一侧和与第一侧相对的第二侧，第二导电类型的第二层和至少一个 在第一侧上形成由第二层包围的第一导电类型的第三层。 在定型RC-IGBT中具有未修饰掺杂的晶片部分形成第一层。 - 之后在第一侧产生第五电绝缘层，其部分地覆盖至少一个第三层，第二层和第一层。 - 在第一侧上形成导电的第四层，其通过第五层与晶片电绝缘。 产生至少一个第三层，第四层和第五层，使得它们在第二层上方形成第一开口。 - 在第一侧上产生第一电接触，该第一电接触与第二层和第三层直接电接触。 - 在第二侧上产生至少第六导电类型的第六层和第一导电类型的至少一个第七层。 至少一个第六和第七层交替地布置在平面中。 - 在第二侧产生第二电触头，其与至少第六和第七层直接电接触。 - 在第四层和第五层的形成之后，通过使用至少第四层和第五层作为第一掩模，通过第一开口注入离子而产生形成为缺陷层的第九层。

公开(公告)号：WO2015028263A1

公开(公告)日：2015-03-05

申请号：PCT/EP2014/066796

申请日：2014-08-05

Applicant: ABB TECHNOLOGY AG

Inventor： BOTAN, Virgiliu ,  VOBECKY, Jan ,  STIEGLER, Karlheinz

IPC: H01L29/74 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/332

CPC classification number: H01L29/744 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/1095 ,  H01L29/66363 ,  H01L29/74

Abstract: The invention relates to a bipolar non-punch-through power semiconductor device (1) and a corresponding manufacturing method. The device comprises a semiconductor wafer (2) and a first electrode (35) formed on a first main side (3) of the wafer and a second electrode (45) formed on a second main side (4) of the wafer opposite the first main side. The wafer comprises a pair of layers of different conductivity types, such as a drift layer (5) of a first conductivity type, and a first layer (6) of a second conductivity type arranged on the drift layer towards the first main side and contacting the first electrode. The wafer comprises an inner region (7) and an outer region (8) surrounding the inner region. The drift layer has a thickness (561) in the inner region greater than, or equal to, a thickness (562) in the outer region. A thickness of the first layer increases linearly over a transition region (11) between the inner region and the outer region from a thickness (615) of a first section (61) of the first layer in the inner region to a maximum thickness (625) in the outer region with a width of the transition region greater than 5 times said thickness of the first section of the first layer.

Abstract translation: 本发明涉及一种双极非穿通功率半导体器件（1）及相应的制造方法。 该装置包括半导体晶片（2）和形成在晶片的第一主侧（3）上的第一电极（35）和形成在与第一主体相对的晶片的第二主侧（4）上的第二电极（45） 主要方面 晶片包括一对不同导电类型的层，例如第一导电类型的漂移层（5）和布置在漂移层上朝向第一主侧的第二导电类型的第一层（6），并且接触 第一个电极。 晶片包括内部区域（7）和围绕内部区域的外部区域（8）。 漂移层在内部区域具有大于或等于外部区域中厚度（562）的厚度（561）。 第一层的厚度从内部区域和外部区域之间的过渡区域（11）在内部区域中从第一层的第一部分（61）的厚度（615）线性上升到最大厚度（625 ），其中过渡区域的宽度大于第一层的第一部分的厚度的5倍。

公开(公告)号：WO2014202750A1

公开(公告)日：2014-12-24

申请号：PCT/EP2014/063016

申请日：2014-06-20

Applicant: ABB TECHNOLOGY AG

Inventor： RAHIMO, Munaf ,  KOPTA, Arnost ,  CORVASCE, Chiara ,  VOBECKY, Jan

IPC: H01L29/861 ,  H01L29/868 ,  H01L29/36

CPC classification number: H01L29/861 ,  H01L29/36 ,  H01L29/868

Abstract: A fast recovery diode (1) is provided, which comprises a wafer (10) having a cathode side (11) and an anode side (12) opposite the cathode side (11), wherein layers are arranged in the wafer in the following order between the cathode side (11) to the anode side (12): an (n-) doped base layer (2), a p doped anode buffer layer (3) with a first maximum doping concentration between 1 * 10 15 cm -3 to 1 * 10 16 cm -3 located up to a first depth (31) between 5 μιτι to 15 μιτι, a (p+) doped anode contact layer (34) with a second maximum doping concentration of 1 * 10 16 cm -3 to 1 * 10 17 cm -3 located up to a second depth (35) of at most 2 μιη, wherein the diode (1) does not comprise a local life time control layer, which is limited in its extension in a direction perpendicular to the anode side (12).

Abstract translation: 提供一种快速恢复二极管（1），其包括具有阴极侧（11）和与阴极侧（11）相对的阳极侧（12）的晶片（10），其中层以下列顺序排列在晶片中 在阴极侧（11）与阳极侧（12）之间：（n）掺杂的基底层（2），掺杂了掺杂的阳极缓冲层（3），第一最大掺杂浓度为1×1015cm-3至1 * 1016厘米3，其位于5微米至15微米之间的第一深度（31），（p +）掺杂阳极接触层（34），第二最大掺杂浓度为1 * 1016厘米3至1 * 1017厘米 -3位于至多2μΩ的第二深度（35），其中二极管（1）不包括本地寿命控制层，其在垂直于阳极侧（12）的方向上被限制在其延伸 ）。

公开(公告)号：WO2009043870A1

公开(公告)日：2009-04-09

申请号：PCT/EP2008/063137

申请日：2008-10-01

Applicant: ABB Technology AG ,  RAHIMO, Munaf ,  VOBECKY, Jan ,  JANISCH, Wolfgang ,  KOPTA, Arnost ,  RITCHIE, Frank

Inventor： RAHIMO, Munaf ,  VOBECKY, Jan ,  JANISCH, Wolfgang ,  KOPTA, Arnost ,  RITCHIE, Frank

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A controlled-punch-through semiconductor device (1) with a four-layer structure comprising layers of different conductivity types and having a collector (2) on a collector side (21) and an emitter (3) on an emitter side (31), which lies opposite the collector side (21) is produced. The steps for producing the semiconductor device are performed in the following order: - on a wafer of a first conductivity type steps for producing layers on the emitter side (31) are performed, - then the wafer is thinned on its second side, - then particles of the first conductivity type are applied to the wafer on the collector side (21) by implantation or deposition of the particles of the first conductivity type for forming a first buffer layer (5), the first buffer layer (5) having a first peak doping concentration (52) in a first depth (51), which is higher than the doping of the wafer, - then particles of a second conductivity type are applied to the wafer on its second side by implantation or deposition for forming a collector layer (6), and - then a collector metallization (7) is formed on the second side. At any stage particles of the first conductivity type are applied to the wafer on its second side by implantation of the particles for forming a second buffer layer (8). The second buffer layer (8) has in a second depth (81) a second peak doping concentration (82), which is lower than the first peak doping concentration (52) of the first buffer layer (5), but higher than the doping of the wafer. There is a third buffer layer (9) arranged between the first depth (51) and the second depth (81) with a minimum doping concentration (92), which is lower than the second peak doping concentration (82) of the second buffer layer (8). At any stage after applying the particles, a thermal treatment for forming the first buffer layer (5), the second buffer layer (8) and/or the collector layer (6) is performed.

Abstract translation: 一种具有四层结构的受控穿透半导体器件（1），其包括不同导电类型的层并且在集电极侧（21）上具有集电极（2）和发射极侧（31）上的发射极（3） 产生与集电体侧（21）相对的位置。 用于制造半导体器件的步骤按以下顺序执行： - 在用于在发射极侧（31）上产生层的第一导电类型步骤的晶片上进行，然后晶片在其第二侧变薄，然后 第一导电类型的颗粒通过注入或沉积用于形成第一缓冲层（5）的第一导电类型的颗粒施加到集电器侧（21）上的晶片，第一缓冲层（5）具有第一 在第一深度（51）中的峰值掺杂浓度（52）高于晶片的掺杂，然后通过用于形成集电极层的注入或沉积将第二导电类型的颗粒施加到晶片的第二侧上 （6），然后在第二面上形成集电体金属化（7）。 在任何阶段，通过注入用于形成第二缓冲层（8）的颗粒，第一导电类型的颗粒在其第二侧施加到晶片上。 第二缓冲层（8）在第二深度（81）具有低于第一缓冲层（5）的第一峰值掺杂浓度（52）的第二峰值掺杂浓度（82），但高于掺杂 的晶片。 在第一深度（51）和第二深度（81）之间设置有第三缓冲层（9），其具有最小掺杂浓度（92），其低于第二缓冲层的第二峰值掺杂浓度（82） （8）。 在施加颗粒之后的任何阶段，进行用于形成第一缓冲层（5），第二缓冲层（8）和/或集电体层（6）的热处理。