公开(公告)号：WO2018089559A1

公开(公告)日：2018-05-17

申请号：PCT/US2017/060727

申请日：2017-11-08

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： LUAN, Harry ,  AXELRAD, Valery ,  CHENG, Charlie

IPC: H01L21/8229 ,  H01L29/66 ,  H01L27/102 ,  H01L21/76

CPC classification number: H01L27/1052 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/8229 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66363 ,  H01L29/66378 ,  H01L29/742 ,  H01L29/749

Abstract: Memory arrays of vertical thyristor memory cells with SiGe base layers are described. The composition of the SiGe can be constant or varied depending upon the desired characteristics of the memory cells. The memory cells allow a compact structure with desirable low voltage operations.

Abstract translation: 描述了具有SiGe基极层的垂直晶闸管存储单元的存储器阵列。 SiGe的组成可以是恒定的或根据存储器单元的期望特性而变化。 存储器单元允许具有期望的低电压操作的紧凑结构。

公开(公告)号：WO2016016427A1

公开(公告)日：2016-02-04

申请号：PCT/EP2015/067653

申请日：2015-07-31

Applicant: ABB TECHNOLOGY AG

Inventor： BELLINI, Marco ,  VOBECKY, Jan

IPC: H01L29/74 ,  H01L29/08

CPC classification number: H01L29/7428 ,  H01L29/0839 ,  H01L29/66363 ,  H01L29/74

Abstract: A thyristor, in particular a phase control thyristor, is disclosed which comprises: a) a semiconductor slab, in particular a semiconductor waver or die, in which a thyristor structure is formed, b) a cathode metallization formed on a cathode region on a cathode side surface of the semiconductor slab, c) a gate metallization formed on a gate region on the cathode side surface of the semiconductor slab, d) a plurality of N discrete emitter shorts, arranged at points P, in the cathode re¬ gion, said points having point locations x,, with i e {1;...; Λ/}, e) the points P, defining a Delaunay triangulation comprising a plurality of trian¬ gles Ty with ye {1;...; M), wherein f ) for a first subset of triangles T/ with / e Si _≡ {1;...; M), g) with each triangle T/ being characterized by a geometric quantity having values qjj with / e Si _≡ {1;...; M), said geometric quantity having a mean value μ, and i) a coefficient of variation of the values qjj with / e Si is smaller than 0.1, preferably smaller than 0.05, and/or ii) an absolute value of a skewedness of the geometric quantities qT,/with / e Si is smaller than 5, preferably smaller than 1, and/or iii) a Kurtosis of the geometric quantities q-r,/ with / e Si is smaller than 20, preferably smaller than 10, and/or iv) for a second subset of triangles Tm with m e S2

Abstract translation: 公开了一种晶闸管，特别是相位控制晶闸管，其包括：a）形成有晶闸管结构的半导体板，特别是半导体流体或管芯，b）形成在阴极上的阴极区上的阴极金属化 半导体板的侧表面，c）形成在半导体板的阴极侧表面上的栅极区上的栅极金属化，d）布置在阴极区中的点P处的多个N个离散发射极短路，所述 点具有点位置x ,,即{1; ...; Λ/}，e）点P，定义一个Delaunay三角剖分，包括多个三角形Ty，你们{1; ...; M），其中f）对于第一子集的三角形T /与/ e Si_≡{1; ...; M），g），其中每个三角形T /的特征在于具有值为qjj的几何量，其中/ e Si_≡{1; ...; M），所述几何量具有平均值μ，i）与/ e Si的值qjj的变化系数小于0.1，优选小于0.05，和/或ii）所述几何量的偏差的绝对值 几何量qT，/ / e Si小于5，优选小于1，和/或iii）几何量qr，/ / / Si的峰值小于20，优选小于10，和/或 iv）对于第二子集的三角形Tm，其中，与S2相对应的几何量qr，m与其平均值偏离大于预定量，特别是大于30％，其中， （1）数量qj，m的标准偏差与me S2的乘数和几何量qi的平均值，/ / e Si小于1，优选小于0.1，和/或（2） 在第二子集中的多个三角形的商和第一子集中的多个三角形的商小于1.0×10 -2，优选小于0.5× 10" 3。 还公开了制造这种晶闸管的方法。

公开(公告)号：WO2012041836A1

公开(公告)日：2012-04-05

申请号：PCT/EP2011/066740

申请日：2011-09-27

Applicant: ABB TECHNOLOGY AG ,  VOBECKY, Jan ,  RAHIMO, Munaf

Inventor： VOBECKY, Jan ,  RAHIMO, Munaf

IPC: H01L29/06 ,  H01L29/747 ,  H01L29/87 ,  H01L29/861 ,  H01L21/329

CPC classification number: H01L29/74 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/102 ,  H01L29/66136 ,  H01L29/66363 ,  H01L29/8613

Abstract: A bipolar non-punch-through power semiconductor device is provided. It comprises a semiconductor wafer (2) and a first electrical contact on a first main side and a second electrical contact on a second main side. The wafer (2) comprises an inner region (22) with a wafer thickness (23) and a termination region (24), which surrounds the inner region (22) and in which the wafer thickness (23) is reduced at least on the first main side with a negative bevel. The semiconductor wafer (2) comprises at least a two-layer structure with layers of different conductivity types: - a drift layer (26) of a first conductivity type, a first layer of a second conductivity type directly connected to the drift layer (26) on the first main side and contacting the first electrical contact, which first layer extends to a first layer depth, and - a second layer of the second conductivity type, which is arranged in the termination region (24) on the first main side up to a second layer depth. The second layer depth is larger than the first layer depth, which first layer depth is at most 45 μm. The doping concentration of the second layer is lower than the doping concentration of the first layer.

Abstract translation: 提供了一种双极非穿通功率半导体器件。 它包括半导体晶片（2）和第一主侧上的第一电触点和第二主侧上的第二电触点。 晶片（2）包括具有晶片厚度（23）的内部区域（22）和围绕内部区域（22）的端接区域（24），并且晶片厚度（23）至少在 第一主面有负斜面。 半导体晶片（2）至少包括具有不同导电类型的层的至少两层结构： - 第一导电类型的漂移层（26），直接连接到漂移层（26）的第二导电类型的第一层 ）并且与第一电极接触（第一层延伸到第一层深度）接触，并且第二导电类型的第二层布置在第一主侧上的端接区域（24）中 到第二层深度。 第二层深度大于第一层深度，第一层深度最大为45μm。 第二层的掺杂浓度低于第一层的掺杂浓度。

公开(公告)号：WO2017042363A1

公开(公告)日：2017-03-16

申请号：PCT/EP2016/071353

申请日：2016-09-09

Applicant: ABB SCHWEIZ AG

Inventor： ARNOLD, Martin ,  VEMULAPATI, Umamaheswara

IPC: H01L29/744 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/1066 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/36 ,  H01L29/41716 ,  H01L29/66363 ,  H01L29/66393 ,  H01L29/744 ,  H01L29/745

Abstract: The invention relates to a turn-off power semiconductor device comprising a plurality of thyristor cells (52), each thyristor cell (52) comprising a cathode region (54a, 54b); a base layer (55); a drift layer (56); an anode layer (58); a gate electrode (510) which is arranged lateral to the cathode region (54a, 54b) in contact with the base layer (55); a cathode electrode (53a, 53b); and an anode electrode (59). Interfaces between the cathode regions (54a, 54b) and the cathode electrodes (53a, 53b) as well as interfaces between the base layers (55) and the gate electrodes (510) of the plurality of thyristor cells (52) are flat and coplanar. In addition, the base layer (55) includes a gate well region (522) extending from its contact with the gate electrode (510) to a depth (d w ), which is at least half of the depth (d c ) of the cathode region (54a, 54b), wherein, for any depth, the minimum doping concentration of the gate well region (522) at this depth is 50 % above a doping concentration of the base layer (55) between the cathode region (54a, 54b) and the gate well region (522) at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side (530) a distance of 2 μιη from the cathode region (54a, 54b). The base layer (55) includes a compensated region (524) of the second conductivity type, the compensated region being arranged directly adjacent to the first main side (530) and between the cathode region (54a, 54b, 54c) and the gate well region (522), wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4.

Abstract translation: 本发明涉及包括多个晶闸管单元（52）的截止功率半导体器件，每个晶闸管单元（52）包括阴极区（54a，54b）; 基底层（55）; 漂移层（56）; 阳极层（58）; 栅极电极（510），其布置在与所述基底层（55）接触的所述阴极区域（54a，54b）的侧面; 阴极电极（53a，53b）; 和阳极电极（59）。 阴极区域（54a，54b）和阴极电极（53a，53b）之间的接口以及多个晶闸管电池（52）的基极层（55）和栅电极（510）之间的界面是平坦的和共面的 。 此外，基极层55包括从其与栅极电极510的接触延伸到深度（dw）的栅极阱区（522），该深度（dw）至少为阴极区域的深度（dc）的一半） （54a，54b），其中，对于任何深度，在该深度处的栅极阱区（522）的最小掺杂浓度高于阴极区（54a，54b）之间的基底层（55）的掺杂浓度的50％ 以及在该深度处和横向位置处的栅极阱区域（522），所述横向位置具有与平行于第一主侧面（530）的平面垂直的投影，与阴极区域（54a，54b）的距离为2微米。 基极层（55）包括第二导电类型的补偿区域（524），补偿区域直接邻近第一主侧（530）设置，并且在阴极区域（54a，54b，54c）和栅极阱 区域（522），其中相对于补偿区域中的净掺杂浓度的第一导电类型杂质的密度为至少0.4。

公开(公告)号：WO2015154908A1

公开(公告)日：2015-10-15

申请号：PCT/EP2015/053697

申请日：2015-02-23

Applicant: ABB TECHNOLOGY AG

Inventor： RAVENER, Hendrik ,  WIKSTROEM, Tobias ,  AMSTUTZ, Hermann ,  MEIER, Norbert

IPC: H01L23/051 ,  H01L23/31

CPC classification number: H01L29/745 ,  H01L21/565 ,  H01L23/051 ,  H01L23/3185 ,  H01L29/45 ,  H01L29/66363 ,  H01L29/7416 ,  H01L29/7424 ,  H01L29/744 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a turn-off power semiconductor device (1) having a wafer (10) with an active region and a termination region surrounding the active region, a rubber ring (70) as an edge passivation for the wafer (10) and a gate ring (60) placed on a ring-shaped gate contact (40) on the termination region for contacting the gate electrodes of at least one thyristor cell formed in the active region of the wafer. In the turn-off power semiconductor device (1) of the invention, the outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring (70). In the invention the area consumed by the ring-shaped gate contact (40) on the termination or edge region can be minimized. The upper surface of the gate ring (60) and the upper surface of the rubber ring (70) form a continuous surface extending in a plane parallel to the first main side (11) of the wafer (10). In a method for manufacturing the device, the gate ring (60) is used as an inner sidewall of a mold for molding the rubber ring (70).

Abstract translation: 本发明涉及一种具有晶圆（10）的截止功率半导体器件（1），其具有有源区和围绕有源区的端接区，作为用于晶片（10）的边缘钝化的橡胶环（70） 以及放置在终端区上的环形栅极接触件（40）上的栅极环（60），用于接触形成在晶片有源区域中的至少一个晶闸管电池的栅电极。 在本发明的关断功率半导体装置（1）中，门环的外周面与橡胶环接触，以限定橡胶环（70）的内边界。 在本发明中，环形门接触件（40）在终端或边缘区域上消耗的面积可以最小化。 闸环（60）的上表面和橡胶环（70）的上表面形成在与晶片（10）的第一主侧（11）平行的平面中延伸的连续表面。 在制造该装置的方法中，门环（60）用作模制橡胶环（70）的模具的内侧壁。

公开(公告)号：WO2015047671A1

公开(公告)日：2015-04-02

申请号：PCT/US2014/053720

申请日：2014-09-02

Applicant: INTEL CORPORATION

Inventor： DOYLE, Brian S. ,  SHAH, Uday ,  KOTLYAR, Roza ,  KUO, Charles C.

IPC: H01L29/786 ,  H01L29/788 ,  H01L21/336 ,  H01L21/20

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4983 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/7391 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7848

Abstract: Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

Abstract translation: 描述垂直晶体管器件。 例如，在一个实施例中，垂直晶体管器件包括设置在衬底上的外延源半导体区域，设置在源极半导体区域上的外延沟道半导体区域，设置在沟道半导体区域上的外延漏极半导体区域和栅电极 区域围绕半导体沟道区域的侧壁。 至少一个半导体区域的组合物沿着相对于衬底的表面垂直的纵向轴线变化。

公开(公告)号：WO2015028263A1

公开(公告)日：2015-03-05

申请号：PCT/EP2014/066796

申请日：2014-08-05

Applicant: ABB TECHNOLOGY AG

Inventor： BOTAN, Virgiliu ,  VOBECKY, Jan ,  STIEGLER, Karlheinz

IPC: H01L29/74 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/332

CPC classification number: H01L29/744 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/1095 ,  H01L29/66363 ,  H01L29/74

Abstract: The invention relates to a bipolar non-punch-through power semiconductor device (1) and a corresponding manufacturing method. The device comprises a semiconductor wafer (2) and a first electrode (35) formed on a first main side (3) of the wafer and a second electrode (45) formed on a second main side (4) of the wafer opposite the first main side. The wafer comprises a pair of layers of different conductivity types, such as a drift layer (5) of a first conductivity type, and a first layer (6) of a second conductivity type arranged on the drift layer towards the first main side and contacting the first electrode. The wafer comprises an inner region (7) and an outer region (8) surrounding the inner region. The drift layer has a thickness (561) in the inner region greater than, or equal to, a thickness (562) in the outer region. A thickness of the first layer increases linearly over a transition region (11) between the inner region and the outer region from a thickness (615) of a first section (61) of the first layer in the inner region to a maximum thickness (625) in the outer region with a width of the transition region greater than 5 times said thickness of the first section of the first layer.

Abstract translation: 本发明涉及一种双极非穿通功率半导体器件（1）及相应的制造方法。 该装置包括半导体晶片（2）和形成在晶片的第一主侧（3）上的第一电极（35）和形成在与第一主体相对的晶片的第二主侧（4）上的第二电极（45） 主要方面 晶片包括一对不同导电类型的层，例如第一导电类型的漂移层（5）和布置在漂移层上朝向第一主侧的第二导电类型的第一层（6），并且接触 第一个电极。 晶片包括内部区域（7）和围绕内部区域的外部区域（8）。 漂移层在内部区域具有大于或等于外部区域中厚度（562）的厚度（561）。 第一层的厚度从内部区域和外部区域之间的过渡区域（11）在内部区域中从第一层的第一部分（61）的厚度（615）线性上升到最大厚度（625 ），其中过渡区域的宽度大于第一层的第一部分的厚度的5倍。

公开(公告)号：WO2013049850A2

公开(公告)日：2013-04-04

申请号：PCT/US2012058361

申请日：2012-10-01

Applicant: PAKAL TECHNOLOGIES LLC

Inventor： BLANCHARD RICHARD A ,  AKIYAMA HIDENORI ,  TWORZYDLO WOYTEK

CPC classification number: H01L29/7455 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42308 ,  H01L29/66363

Abstract: Methods and systems for a gate-controlled thyristor which switches between narrow-base operation in the ON state and wide -base operation in the OFF state, and which can only sustain latch-up in the narrow-base ON state.

Abstract translation: 用于门控晶闸管的方法和系统，其在ON状态下的窄基操作和OFF状态下的宽基操作之间切换，并且其只能在窄基ON状态下维持闭锁。

公开(公告)号：WO02084743A8

公开(公告)日：2003-01-09

申请号：PCT/DE0201196

申请日：2002-04-03

Applicant: BOSCH GMBH ROBERT ,  PLIKAT ROBERT ,  FEILER WOLFGANG

Inventor： PLIKAT ROBERT ,  FEILER WOLFGANG

IPC: H01L21/332 ,  H01L29/06 ,  H01L29/10 ,  H01L29/745 ,  H01L29/749

CPC classification number: H01L29/66363 ,  H01L29/0634 ,  H01L29/102 ,  H01L29/7455 ,  H01L29/749

Abstract: The invention relates to a power semiconductor component, e.g. an emitter switched thyristor comprising an anode contact at the rear (502), an emitter region (505) of a first conductivity type (p ) (504, 514, 540) and a drift region, which extends partially to the front surface; a front MOS control structure (503, 506, 560, 508, 580, 509); and a front cathode contact (501). The drift region (504, 514, 540) has a first drift zone (540) of the second conductivity type (n ), a second drift zone (504) of the second conductivity type (n) and a third drift zone (514) of the first conductivity type (p). The first drift zone (540) is a buried zone. The second drift zone (504) connects the front surface with the first drift zone (540). The third drift zone (514) connects the first and/or the second body region (508, 580) with the first drift zone (540).

Abstract translation: 本发明例如，一个半导体功率器件 发射器 - 切换 - 在第一导电类型（P +）（504，514，540），其部分地延伸到前表面的后部晶闸管阳极接触（502）和发射极区（505）; 前侧MOS控制结构（503，506，560，508，580，509）; 前侧阴极接触（501）。 漂移区（504，514，540）包括所述第二导电类型（n）时，第二导电类型（n）和所述第一导电型（P）的第三漂移区（514）的第二漂移区（504）上的第一漂移区（540） ， 第一漂移区（540）是一个隐埋区。 的第二漂移区（504）与所述第一漂移区（540）连接所述前表面。 第三漂移区（514）与所述第一漂移区（540）连接第一和/或第二体区（508，580）。 第二和与漂移区（504）第三。

公开(公告)号：WO1993002474A1

公开(公告)日：1993-02-04

申请号：PCT/DE1992000536

申请日：1992-06-29

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： SIEMENS AKTIENGESELLSCHAFT ,  OPPERMANN, Klaus-Günter ,  STOISIEK, Michael

IPC: H01L29/08

CPC classification number: H01L29/66333 ,  H01L29/0834 ,  H01L29/66363 ,  H01L29/66378

Abstract: The invention relates to a power semiconductor with four zones in which an emitter zone (A) has at least one emitter region (4) and at least a first part (5) of the extractor structure (AS) and in which the first part of the extractor structure is electrically connected to a main electrode (7) via a second part (6) of the extractor structure (AS). The invention prevents the ignition of a parasitic thyristor, for instance with insulated-gate bipolar transistor (IGBT) and gives a pentode-like output characteristics in thyristors.