公开(公告)号：WO2018182605A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/024961

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： THEN, Han, Wui ,  FISCHER, Paul, B. ,  RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L29/7786 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462

Abstract: Semiconductor devices including III-N transistors adjacent to III-N substrate taps extending from a group IV heteroepitaxial growth substrate are described. In embodiments, GaN mesas that are to host conductive substrate taps are grown concurrently with GaN mesas that are to host transistors. A GaN mesa for a substrate tap is then selectively doped, for example with a masked implant. An intrinsic GaN mesa for a transistor is then selectively processed, for example to form a transistor channel. Heavily doped semiconductor may then be grown on all GaN mesas and contact metallization landed on the heavily doped semiconductor. Backend interconnect levels may then be successively landed on the substrate tap to maintain an electrical path to the substrate sufficient to mitigate charging-related damage to the transistors during backend processing.

公开(公告)号：WO2019139573A1

公开(公告)日：2019-07-18

申请号：PCT/US2018/013151

申请日：2018-01-10

Applicant: INTEL CORPORATION

Inventor： FISCHER, Paul, B. ,  THEN, Han, Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  LIN, Kevin

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

Abstract: Techniques are disclosed for fabricating airgaps to explicitly suppress parasitic electrical pathways between devices through the use of selectively etchable materials or layers. Using such features, relatively high device densities can be achieved while still suppressing crosstalk between devices. In particular, selective etchable layers are incorporated into a fabrication process. Lithographically defined access holes or trenches are introduced to facilitate the selection of etchable regions.

公开(公告)号：WO2017111805A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000347

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： BLOCK, Bruce, A. ,  FISCHER, Paul, B. ,  TANZI, Nebil ,  CHANCE, Gregory ,  THEN, Han, Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko

IPC: H03H3/007 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H03H3/0073 ,  H03H3/02 ,  H03H9/0557 ,  H01L2224/13099

Abstract: Techniques to fabricate an RF filter using 3 dimensional island integration are described. A donor wafer assembly may have a substrate with a first and second side. A first side of a resonator layer, which may include a plurality of resonator circuits, may be coupled to the first side of the substrate. A weak adhesive layer may be coupled to the second side of the resonator layer, followed by a low-temperature oxide layer and a carrier wafer. A cavity in the first side of the resonator layer may expose an electrode of the first resonator circuit. An RF assembly may have an RF wafer having a first and a second side, where the first side may have an oxide mesa coupled to an oxide layer. A first resonator circuit may be then coupled to the oxide mesa of the first side of the RF wafer.

Abstract translation: 描述了使用三维岛集成制造RF滤波器的技术。 施主晶圆组件可具有具有第一侧和第二侧的衬底。 可以包括多个谐振器电路的谐振器层的第一侧可以耦合到衬底的第一侧。 弱粘合剂层可以耦合到谐振器层的第二侧，接着是低温氧化物层和载体晶片。 谐振器层的第一侧中的空腔可以暴露第一谐振器电路的电极。 RF组件可以具有RF晶片，该RF晶片具有第一侧和第二侧，其中第一侧可以具有耦合到氧化物层的氧化物台面。 然后可以将第一谐振器电路耦合到RF晶片的第一侧的氧化物台面。

公开(公告)号：WO2014051977A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/058796

申请日：2013-09-09

Applicant: INTEL CORPORATION

Inventor： ZILLMANN, Uwe ,  SCHAEFER, Andre ,  SARASWAT, Ruchir ,  KAMGAING, Telesphor ,  FISCHER, Paul, B. ,  DROEGE, Guido

IPC: H01L23/48

CPC classification number: G06F1/3296 ,  H01L2924/0002 ,  H05K1/0262 ,  H05K1/165 ,  Y02D10/172 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate. In further embodiments, integrated circuitry on a same substrate as the magnetically enhanced inductor, or on another substrate stacked thereon, completes the VR and/or is powered by the VR circuitry.

Abstract translation: 在芯片级与微电子器件集成的磁性增强型电感器。 在实施例中，磁增强电感器包括具有填充金属的贯穿衬底通孔（TSV），以承载靠近设置在TSV通过的衬底上的磁性层的电流。 在某些磁增强电感器实施例中，TSV填充金属设置在衬在TSV内的磁性材料内。 在某些磁增强电感器实施例中，磁增强电感器包括靠近基板一侧的磁性材料层设置的多个互连TSV。 在实施例中，设置在衬底的第一侧上的电压调节电路与利用穿过衬底的TSV的一个或多个磁增强电感器集成。 在另外的实施例中，在与磁增强电感器相同的衬底上或在其上堆叠的另一衬底上的集成电路完成VR和/或由VR电路供电。

公开(公告)号：WO2019032100A1

公开(公告)日：2019-02-14

申请号：PCT/US2017/046009

申请日：2017-08-09

Applicant: INTEL CORPORATION

Inventor： LIN, Kevin, L. ,  FISCHER, Paul, B. ,  THEN, Han, Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  BAN, Ibrahim

IPC: H01L27/06 ,  H01L21/768

Abstract: Disclosed herein are integrated circuit (IC) components with substrate cavities, as well as related techniques and assemblies. In some embodiments, an IC component may include a substrate, a device layer on the substrate, a plurality of interconnect layers on the device layer, and a cavity in the substrate.

公开(公告)号：WO2017111792A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000306

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： MUELLER, Brennen, K. ,  MORROW, Patrick ,  JUN, Kimin ,  FISCHER, Paul, B. ,  PANTUSO, Daniel

IPC: H01L21/768 ,  H01L21/60 ,  H01L23/48

CPC classification number: H01L21/76251 ,  H01L21/76838 ,  H01L23/485 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L27/1203 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48105 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/73257 ,  H01L2924/014

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

Abstract translation: 包括电路结构的装置，所述电路结构包括器件层; 在器件层的第一侧上的一个或多个导电互连级，并且耦合到晶体管器件中的一些; 以及衬底，所述衬底包括耦合到所述一个或多个导电互连层的导电硅通孔，使得所述一个或多个互连层位于所述硅通孔和所述器件层之间。 一种方法，包括：在衬底上形成多个晶体管器件，所述多个晶体管器件限定器件层; 在所述器件层的第一侧上形成一个或多个互连层; 去除一部分基板; 以及将硅通孔耦合到所述一个或多个互连级，使得所述一个或多个互连级设置在所述器件层和所述硅通孔之间。

公开(公告)号：WO2017105471A1

公开(公告)日：2017-06-22

申请号：PCT/US2015/066501

申请日：2015-12-17

Applicant: INTEL CORPORATION

Inventor： LILAK, Aaron, D. ,  MEHANDRU, Rishabh ,  KENNEL, Harold, W. ,  FISCHER, Paul, B. ,  CEA, Stephen, M.

IPC: H01L29/78 ,  H01L21/336 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L21/76224 ,  H01L24/16 ,  H01L29/78 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/14335 ,  H01L2924/15311 ,  H01L2224/13099

Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于集成电路（IC）的器件和相关配置的背面隔离的技术。 IC可以包括形成在半导体衬底上的多个器件（例如，晶体管）。 半导体衬底可以包括其上形成有一个或多个器件的衬底区域。 沟槽可以设置在半导体衬底上的器件之间。 衬底区域之间的半导体衬底的部分可被去除以暴露相应的沟槽并形成隔离区域。 绝缘材料可以形成在隔离区中。 其他实施例可以被描述和/或要求保护。